Santa Cruz, Calif. New mathematical approaches that promise up to 40 percent savings in silicon area will become available to a broader audience this week, as intellectual-property (IP) startup Arithmatica Inc. rolls out its first EDA tools.
Arithmatica (Menlo Park, Calif.) is the provider of the CellMath IP libraries, which represent data path functions for graphics and DSP applications. This week it will add CellMath Designer, a data path synthesis tool, and CellMath Builder, a tool that configures a library of floating-point functions.
"Now we can deliver the proprietary technology we developed to represent math functions in silicon through EDA tools," said David Burow, Arithmatica's chairman. "It's really just a more efficient delivery for our technology."
The CellMath IP products are claimed to deliver speed improvements of 15 to 20 percent. In math-intensive applications like graphics and multimedia, CellMath promises to reduce silicon area by 15 to 40 percent and to reduce pipeline depth by 25 to 33 percent.
CellMath Designer is a data path synthesis tool aimed at RTL designers. It supports integer, fixed-point and carry-save arithmetic, configurable floating-point functions, a timing engine, automatic pipelining, logic optimization based on multiple microarchitectures, and operator merging and logic sharing across the entire data path.
Designers describe the data path using a script and choose constraints. Using currently available standard-cell libraries, the tool creates an optimized data path block, Burow said. Outputs include a gate-level netlist, a bit-accurate C model, a bit-accurate Verilog RTL model and a hierarchical gate netlist that can be used for formal verification.
While general-purpose synthesis tools can synthesize data paths, CellMath Designer offers better power, performance and area, Burow said. "We still recommend people run standard synthesis tools on the output to improve the control logic. We're not trying to replace anybody's general-purpose tools."
The input to CellMath Designer is provided in a proprietary C++ language that Burow said is "very Verilog HDL-like and very powerful, with data types not available in HDLs." Many designers have resisted tools with proprietary input languages, but Burow isn't worried. "It may potentially limit some use, but most of our customers see it as an advantage," he said.
Users provide a timed description in this C++ language. The tool can perform resource sharing and pipelining. It thus has some of the attributes of behavioral synthesis as well as RTL synthesis, Burow noted.
The CellMath Builder tool has a narrower focus, Burow said. Its purpose is to accept a wide variety of parameters and to create a set of mathematical primarily floating-point functions. It takes into account user performance goals and options such as bit width, internal accuracy and pipeline stages.
"We've found that the floating-point functions generated by the current set of tools are not that efficient," Burow said. "We created this tool to generate mathematical building blocks that people can instantiate in their designs for building larger floating-point functions."
The tools are available now. Annual fees are $129,000 for CellMath Designer and $89,000 for CellMath Builder.