Hillsboro, Ore. Lattice Semiconductor Corp. has released for its recently announced LatticeXP field-programmable gate array (FPGA) family the first set of IP modules that address the needs of the consumer, computing and communications markets.
Easily integrated into the ispLEVER design tool suite, the IP cores include a 10/100 Ethernet MAC, 1-Gbit Ethernet MAC, PCI, multi-channel DMA controller, FCRAM controller, and DDR controller.
Throughout the year, Lattice will continue to expand the LatticeXP IP portfolio with new ispLeverCORE modules, complemented by IP cores from third-party partners and free, industry-standard reference designs.
"These IP modules, coupled with the unique, non-volatile architecture of our LatticeXP FPGAs, reduce overall design complexity, allow designers to focus on their unique design concerns, and consequently, accelerate our customers' time to market," said Stan Kopec, vice president of corporate marketing.
Free reference designs complement the ispLeverCORE IP cores and support a number of functions. The reference designs are available now and come with either source code or netlist: QDR II SDRAM controller, SDR SDRAM controller, I²C bus master controller, 1553 data bus encoder/decoder, RGMII to GMII bridge, and POS PHY Level 3 link.
IP evaluation packages are available now on the company's Website for immediate download at no charge. Each evaluation package contains a model for functional simulation and an evaluation netlist for fitting purposes and static timing analysis.
Click here for data sheets and user manuals: www.latticesemi.com/ip
See related story: www.eeproductcenter.com/pld-fpga/brief/showArticle.jhtml?articleID=163105230
Lattice Semiconductor Corp., 1-503-268-8000, www.latticesemi.com