SANTA CRUZ, CALIF. — Built-in self-test offers high fault coverage for a range of potential defects, but it has been difficult to implement. LogicVision Inc. promises to change that this week with its LV2005 release, moving logic and memory BIST insertion up to the register-transfer level.
It's all part of a company refocusing, said Jim Healy, LogicVision's president and CEO. While the company's BIST intellectual property (IP) and tooling have been adopted by many chip design companies, the scheme has been relegated to a high-end niche, he said.
BIST "was done at the gate level, and there were other issues in terms of automation," said Healy. "So we took our field-proven technology and did some things to make it easy to use and implement."
The LV2005 release now includes rule checkers, RTL test insertion and a more automated approach to timing closure.
It also adds some mixed-signal BIST capabilities for components such as phase-locked loops, Healy said.
LV2005 represents LogicVision's complete product line. It includes ETCreate, which embeds test capabilities; ETAccess, which runs on the automatic test equipment to provide data logging and diagnostics; and SiVision, a parametric analysis capability that helps improve yield.
Many of the changes revolve around ETCreate, said Steve Pateras, senior director at LogicVision. The product implements the company's new RTL design flow using three main components. The first is ETChecker, which analyzes the RTL design for rule violations and extracts the information that LogicVision needs to add embedded test. Pateras said ETChecker can run on a 30 million- to 40 million-gate design in one or two hours.
The second component, ETPlanner, is a new test resource planning utility. Based on information extracted from ETChecker as well as user constraints such as power and test time, ETPlanner determines the embedded-test resources that are needed to meet the constraints. The end result, said Pateras, is a complete test plan showing how many BIST controllers will be installed and where they will go. This process takes one to two hours.
Finally, a new module called ETAssemble uses the planning data from ETPlanner to generate LogicVision test IP and integrate it into the RTL code. This also takes one to two hours, Pateras said.
The LV2005's "burst mode" test-timing architecture lets users implement at-speed tests in a less intrusive way, he said. It distributes timing control into local clock domains and lessens requirements for high-speed test signals.
A new capability is said to test any number of serdes channels on any frequency by embedding BIST around the serdes blocks. "We can test to subpicosecond accuracy in milliseconds," Pateras said.
Behind the LV2005 enhancements, said Healy, is LogicVision's intention to make BIST a more widespread technology. "We've spent a lot of time with customers, and our goal has been to refocus the company in the areas of ease of use and customer satisfaction," he said.