SAN FRANCISCO FPGA-based electronic system level (ESL) design provider S2C has introduced new interconnect technology designed to enable system-on-chip (SoC) design using plug-and-play intellectual property (IP) modules.
According to S2C, the new testable, analyzable, integratable (TAI) technology can accelerate SoC time-to-market by three to six months.
(San Jose, Calif.) said the patent-pending TAI technology is designed to speed up the design and validation process, as well as enable concurrent hardware-software design. The plug-and-play IP modules are encrypted, S2C said, giving IP vendors the freedom to widely distribute IP without fear of reverse engineering.
In a statement release Tuesday by SC2, Thomas Huang, chairman and CEO of the company, said the TAI technology targets the prototyping step in ESL design, which must be repeated numerous times.
"We targeted this step as a bottleneck to eliminate since it is just a time-consuming mapping of one representation to another that is unrelated to innovation," Huang said. "To accelerate innovation, the designer must be able to easily access IP and quickly assemble a prototype that enables hardware and software to work together to demonstrate system functionality."
TAI IP technology is supported by S2C's IP Porter FPGA-based ESL design platform. The technology was developed by Huang and Vice President of Engineering Mon-Ren Chene, both co-founders of S2C, the company said.
Full production releases of the IP Porter system and TAI Compiler software are available now. Pricing information was not disclosed.