Mountain View, Calif. Actel Corp.'s latest version of its Libero Integrated Design Environment (IDE) features SmartTime static timing analysis technology to enable field-programmable gate array (FPGA) designers to analyze and manage timing constraints.
SmartTime, the company's powerful new multi-view product, also enables FPGA designers to perform advanced timing verification and predict timing closure by tightly integrating place and route.
The SmartTime Constraints Editor view enables users to list, edit and create precise timing constraints. It includes a graphical user interface (GUI) with visual dialogs that guide users toward capturing their timing requirements and exceptions correctly.
"This new version of our Libero IDE includes significant new functionality for design analysis and timing closure," said Saloni Howard-Sarin, director of antifuse and tools marketing at Actel. "Users are able to apply constraints to their designs, manage and analyze the effects of those constraints and drive their designs efficiently to timing closure, while achieving higher performance."
In Libero 6.2 IDE, the company extended its partnership with Mentor Graphics to include the software maker's ModelSim, a Windows-based simulator for VHDL, Verilog and mixed-language simulation environments, as part of the Libero Gold package. It is available to all Actel customers free of charge.
The Libero 6.2 IDE also includes enhanced synthesis capabilities from Synplicity and physical synthesis features from Magma Design Automation.
Synplicity's Sinplify FPGA synthesis software offers a new capability to forward annotate Synopsys Design Constraints (SDC) and physical constraints. The Libero 6.2 IDE can import user-defined constraints automatically then manage, track and pass them forward to design implementation. This helps designers quickly meet timing closure.
"As a key component of the Libero IDE, the Synplify software will give our joint customers confidence that they can push the performance of advanced FPGAs like Axcelerator and still comfortably meet their time-to-market objectives," said Jeff Garrison, director of marketing for FPGA products at Synplicity.
Libero now runs on Linux and Solaris platforms.
Magma Design Automation's Palace synthesis software now also provides support for Actel's Axcelerator family. The software features advanced technologies such as multi-clock retiming, architecture-specific mapping, and constraint-driven and placement-guided optimization.
"Our fully automated Palace software tool provides at least a one speed-grade performance advantage over other PLD synthesis tools on the market," said Behrooz Zahiri, director of marketing at Magma Design Automation. "Designers using our Palace tool with their Actel Axcelerator-based designs can expect to see at least a ten-percent improvement in speed, allowing users to maximize performance or drop to a lower speed-grade device to save costs, while still meeting performance goals."
The Libero 6.2 IDE is available in a Platinum edition on Windows and Unix platforms, which sell for $2495 and $4995, respectively. The Gold edition is available for free. All editions are one-year renewable licenses.
Actel Corp., 1-650-318-4200, www.actel.com