Palo Alto, Calif.Automatic test equipment maker Agilent Technologies now has a new final-test memory tester targeting MCPs (multi-chip packages) and discrete flash. Dubbed the Versatest Series Model V5500, this ATE system offers a tester-per-site architecture.
What's more, an optional Programmable Interface Matrix can be used to optimize single-insertion testing of MCPs that use multiple memory types (such as a mix of flash, DRAM, and SRAM). This promises very high tester utilization and throughput, factors that can dramatically lower the cost-of-test.
With an amazing 16,384 pins per testhead, Agilent's V5500 with its Programmable Interface Matrix is arguably the highest pin-count tester for final test that's available today.
The V5500's high pin-count is designed to fully use leading-edge x320 handlers at up to 320 NAND devices in parallel. It also enables parallel testing of high-pin-count NOR and MCPs at up to 256 devices in parallel.
"That's much more than any competitor offers," avows Gayn Erickson, VP of Agilent's memory test division. "As such, it can radically reduce the cost-of-test by permitting both high-parallel and single-insertion testing of MCPs. The matrix will let the industry massively adopt complex MCPs. That'll be crucial to the wide availability of third-generation cellphones and advanced consumer electronics."
Indeed, the ongoing trend in handsets toward multimedia applications and miniaturization means that increasing densities and types of memory will continually be squeezed into smaller packages. Cellphone developers are already adopting circuits built with stacked die.
Many of the latest cellphones use MCPs containing a die stack of two to four memories, and some 3G cellphones are currently using a stack of six, with nine on the horizon.
But, while MCPs address density and space concerns for OEMs, they also present challenges for MCP makers and test engineers. Because MCPs typically house multiple memory types, such as combinations of flash and various types of RAM, MCP makers often use multiple testers, each one optimized for a specific memory type.
Regardless of expense, that's usually the only way to test a stack. But, the capital expense of multiple testers can be staggering. Falling average selling prices of end products hide the increases in test costsbut they don't reduce it!
What's more, different memories have different test times, and it's not unusual for tester resources to sit idle waiting for long tests to finish. You may also have to test memories sequentially, with idle pins. Testers aren't optimized for discrete flash either.
Add to that the expense of an ATE system's load boards. Typically, each tester in a multiple tester suite requires a different load board. As the rate of technology change increases, the consumable expense related to load boards can become significant.
Also, more relays in a load board increases its cost, and boards must be re-designed for each new MCP. Moreover, the number of relays (more than 3,000 for high-parallel test isn't unusual) impacts reliability.
Test program generation is also typically more complex with a shared resource architecture than with a tester-per-site architecture. Single insertion MCP test, with its inherent serial test of individual die, increases complexity even further. Quick re-use of existing individual die programs for an MCP program is typically not an option because of shared resource optimizations made in a program.
Finally, In addition, multi-insertion test usually introduces yield loss with each insertion. That's yet another factor that contributes to the high cost-of-test.
A Single Insertion
Enter Agilent's new Versatest Series Model V5500 with greater than 8500 signal-pins/head. With that, Erickson contends that no other tester can perform high-parallel test of complex MCPs with a single insertion like the V5500 can. "The V5500 lowers capital expense and test time through optimized single-insertion test of all MCP memories," he says.
"That's significant as single-insertion test requires high I/O pin-count testers, and the capability to fully test all memory devices present on an MCP."
Erickson emphasizes that a tester must also accommodate different pin, power, speed, and accuracy requirements of each memory die. "Other testers," he says, "optimized for a single type of memory die, or without the performance to test all the memories in a stack, force additional insertions on two or more testers."
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"When testing MCPs, each die is tested serially," adds Erickson. "Only a subset of the total I/O pins required to test the high-pin-count MCP is used to test each individual die. With other testers, resource utilization is low because most of the expensive I/O hardware required to meet the MCP's pin-count sits idle. The V5500 with the optional Matrix's 16,384 pins per testhead makes it capable of testing complex MCPs, with up to 256 pins, at 64 to 256 devices in parallel."
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The V5500 with the Programmable Interface Matrix also addresses the need for testing discrete memories, providing a high-parallel low-cost-of-test approach for NOR and NAND devices. In its high-parallel test mode, the Matrix delivers a 4X increase in parallelism when testing flash. High-pin-count NOR flash can be tested at up to 256 devices in parallel, and NAND flash can be tested at up to 320 in parallel, using a leading-edge x320 handler.
The Versatest memory test products also offer an end-to-end approach, useful from engineering development through to high-volume manufacturing, for both wafer-sort and final test.
Pricing for a V5500 starts at about $1.3 million for a system capable of testing 256 devices in parallel. Agilent says units are available right now for immediate shipment.
Click here for technical details and to access a Matrix demo.
For more details, contact Agilent Technologies, 395 Page Mill Rd., Palo Alto, Calif. 94303. Phone: 800-829-4444. Fax: (650) 752-5300.
Agilent Technologies, 800-829-4444, www.agilent.com/see/memorytest