Dallas, Tex.In an move to expand its portfolio of PCI Express (PCIe) products, Texas Instruments Inc. has released the third generation of its discrete PCIe physical layer (PHY) chip.
The XI01100 PHY IC is aimed at interfacing with ASICs and low-cost FPGAs in PC add-in cards, communications and test equipment, servers and other embedded system applications.
It XI01100 is a discrete x1 PCIe 1.1 compliant PHY that meets the jitter requirements in the 1.1 specification. It supports both 8-bit and 16-bit parallel interfaces based on Santa Clara, Calif.-based Intel Corp.’s PIPE (PHY Interface for PCI Express) architecture. PIPE defines the standard interface between PCIe MAC and physical coding sublayer.
The XI01100 was designed, however, with minor enhancements that allow for lower power consumption and a simplified interface.
TI would not provide further details on the XI01100 PHY IC’s technical features.
The latest version has been enhanced to support source synchronous clocking on both the Tx and Rx paths, which eases board layout constraints.
“It is an optimized solution so it can fit in a smaller package size versus the current test chip” said Brian Whitaker, product marketing engineer, connectivity solutions group. Since the XI01100 is PCIe 1.1 compliant, TI is “very confident in the robustness of the third generation chip.”
The device supports multiple PCIe reference clocks, providing 100-MHz differential and 125-MHz single-ended. It also supports enhanced low-power states by turning off clock in L1. It offers an access speed of 2.5-Gbits/s and offers a digital 8-bit I/F.
The XI01100 is expected to sample in the fourth quarter of this year. Production volumes will be available in the first quarter of 2006. In 250,000-unit quantities, the device will cost approximately $7 each.
Texas Instruments Inc. 1-972-644-5580, www.ti.com.