Mountain View, CA Cavium Networks’ new Octeon EXP microprocessor embeds up to sixteen MIPS64-based cores in a single chip to reduce cost and increase performance and functionality for converged control and data-plane applications. The processors scale from multi-100 Mbps rates to multi-Gigabit rates. Target applications for the Octeon EXP include routers, intelligent switches, multi-service access equipment, storage servers, multi-protocol storage switches, and other Wireless Infrastructure Equipment.
The processor family offers a complete software and footprint compatible architecture that provides from 4 to 16 MIPS64-based cores on a single chip with an array of integrated networking interfaces, memory controllers and co-processors to enable 2Gbps to 10Gbps of application performance at under 10Watts to 30Watts, according to Cavium.
Traditionally, control plane and data plane processing architectures have been fragmented across performance ranges requiring disparate software architectures and multiple software development efforts, according to Cavian. In low-end routers for example, control and data plane functions are implemented in a single CPU, called a communication processor. In mid-range to high-end modular routers, multi-service access equipment and wireless base station equipment, the control and data plane processing is done in multiple chips consisting of a general purpose processor, micro-code based network processor and/or fixed function ASICs.
The Octeon EXP provides 19.2 Billion instructions/s of general-purpose processing available across 16, dual-issue, memory coherent, MIPS64 Release 2 based cores. Each 600MHz MIPS64 core in OCTEON is built from the ground-up with additional instructions for packet acceleration and a 32K I-cache, 8K D-cache, 32 entry TLB and 2KB write-back buffer.
For high-performance network throughput, Octeon EXP integrates dedicated packet processors for layer 2 – layer 4 parsing, error checking, tagging and memory allocation. Additionally, processor has three high-performance, on-chip memory controllers.
The first memory interface supports 144 bit wide, ECC-protected DDR II DRAM up to 800Mbps data-rate, with capacity of up to 16GB and bandwidth greater than 100 Gbits/sec. Two additional memory interfaces support 18 bit wide low-latency RLDRAM2 / FCRAM2, with low latency access and capacity of up to 1GB. This same memory interfaces can be used to connect a TCAM(s) for offloading lookups to an external hardware device. For higher layer data-plane processing, the processor has dedicated hardware for TCP acceleration and flow management to scale performance across multiple cores.
To reduce bill or material cost, Octeon has integrated multiple standard external networking interfaces with 4 to 8 Gigabit Ethernet ports (RGMII) or dual SPI-4.2 interfaces along with a host/slave PCI-X 64bit 133MHz interface that can be used as both a data and control interface. The processor also offers auxiliary interfaces such as GPIO, Flash, MDIO, dual UARTs and 2wire serial interfaces.
Standard software programming model includes C/C++, MIPS64 and MIPS32 compatibility, Linux operating system support, GNU tool-chain and development environment along with support for third party commercial operating systems and tools for porting proprietary operating systems.
There are 5 different parts available in the OCTEON EXP family. The CN38xx family offers 4, 8, 12 or 16 MIPS64-based cores in a footprint compatible package. Production pricing for the OCTEON EXP 38xx family ranges from $350 for a four-core chip to $650 for the sixteen core device in 10K unit quantities. The family of processors is sampling today along with the development kit including Simulator, tool-chain and reference applications.
Cavium Networks, (650) 623-7033
For more information, please visit: www.caviumnetworks.com.