In a simultaneous release on their respective web sites, IBM, Sony, Sony Entertainment and Toshiba announced the availability of key documents that describe technical details of the Cell Broadband Engine architecture the companies have been working on for the last three years or more.
The documents are available at http://cell.scei.co.jp and www.ibm.com/developerworks/power/cell
The documents go into much greater detail than the high level technical specifications released in papers delivered at San Francisco's International Solid State Circuit Conference (ISSCC) in February of this year.
The companies said the reason for the release was to “establish a thriving community of interest and innovation around Cell, allowing all interested parties to rapidly evaluate and utilize Cell technology.”
The five documents available now for download include information on:
(1) The Cell Broadband Engine Architecture, which defines a processor structure directed toward distributed processing and multimedia applications, including the control processor based on the Power Architecture, augmented with multiple high- performance SIMD Synergistic Processor Units and the set of DMA commands for efficient communications among processing elements.
(2) The Synergistic Processor Unit Instruction Set Architecture (SPU ISA), which discloses the details of the high performance SIMD RISC processor designed to accelerate media and streaming applications for systems based upon the Cell Broadband Engine Architecture.
(3) The SPU C/C++ Language Extensions, which includes information on the extensions to the C/C++ languages that will be useful when writing SPU programs as well as SPU-specific datatype definition and intrinsics that directly map to machine instructions.
(4) The SPU Application Binary Interface Specification.
(5) The SPU Assembly Language Specification.
Toshiba is still in the process of preparing additional documents relating to the Cell Processor Architecture, including proposals which combine Cell with other resources the company has developed. These resources include detailed developer information on its’ ‘Super Companion Chip' dedicated peripheral LSI, software, reference sets and a system development environment. When completed these will be posted on the Toshiba web site.
Developers wishing to understand the Cell hardware architecture’s underlying programming and software model and the implications of the new architecture should refer to key U.S. patents issued to, or in the process of being issued to, the companies between June and December of last year, including:
Patent Number 6,826,662: System and method for data synchronization for a computer architecture for broadband networks.
Patent Number 6,809,734: Resource dedication system and method for a computer architecture for broadband networks.
Patent Application 20050138325: Multi-chip module with third dimension interconnect.