Tokyo, Japan - In a development that could have significant impact of a wide range of memory-intensive embedded System-on-Chip designs, Renesas Technology Corp. today announced that it has built a high-density capacitorless twin-transistor RAM (TTRAM) that achieves both high-speed operation and low power consumption.
Neither SRAM or DRAM, the TTRAM described by Renesas researchers at the 2005 IEEE Custom Integrated Circuits Conference, has been built with 65nm (nanometer) generation and subsequent silicon-on-insulator (SOI) CMOS semiconductor processes.
In a 2Mbit test chip fabricated with a 130nm SOI-CMOS process, the TTRAM has achieved 250MHz operation in continuous data output mode and 133MHz in random access operation, while dissipating an active power of only 148mW, nearly 43 percent less than a conventional Renesas 130nm CMOS process embedded DRAM.
Unlike a traditional DRAM cell which requires a specially shaped capacitor, the
TTRAM memory cell doesn't use a capacitor, so it is compatible with shrinks of process technology that make transistors smaller and faster. On the 2Mbit test chip, the TTRAM cell size is 0.33um2, over five percent smaller than the 0.35um2 cell size of a 130nm CMOS process embedded DRAM test chip fabricated separately by Renesas.
The memory cell is a floating-body type capacitorless design in which two transistors are serially connected on an SOI substrate. One is an access transistor, while the other is used as a storage transistor and fulfills
the same function as the capacitor in a conventional DRAM cell.
Data reads and writes are performed according to the conduction state of the access transistor and the floating-body potential state of the storage transistor. Because the TTRAM memory cell operations don't require a step-up
voltage or negative voltage, as DRAM cells do, the new cell design suitable for use with future finer processes and lower operating voltages.
In the TTRAM, a read signal from a memory cell appears as a difference in the transistor on-current. A current-mirror type sense amplifier detects this difference at high speed, using a reference memory cell that allows reliable
identification of the 0 and 1 data levels. This reading method significantly decreases power consumption by eliminating the charging and discharging of bit lines, operations required for reading DRAM memory cells.