Richardson, TexasA product called DFT Analyzer from ASSET InterTech, Inc., a maker of IEEE-1149.1/JTAG boundary-scan test and ISP (in-system programming) tools, promises to reduce manufacturing and test costs when it debuts early next year. ASSET's DFT Analyzer will validate boundary-scan DFT (design-for-test) in a circuit board designbefore any prototypes are assembled.
In addition, DFT Analyzer will determine the extent of a design’s boundary-scan test coverage, and recommend changes that would increase coverage. All too often, a new product will be delayed as it moves out of development and into manufacturing. That's typically because a circuit board can't be adequately tested and has to be re-designed. Without adequate test coverage, you can't be assured of a product’s quality.
That's where ASSET InterTech's DFT Analyzer comes in. It will alleviate some schedule risks, and reduce test and prototyping costs. It will do that by alerting you early in a design cycle, when it's easier and less costly to design-in testability.
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ASSET says its DFT Analyzer is the outcome of extensive research and feedback from manufacturers. Users wanted a boundary-scan DFT tool that could be incorporated into the typical design process for boards, and complement other EDA
(electronic design automation) systems.
Three Tools In One
DFT Analyzer will be made up of three tools used at different stages in product development. First, as schematics are developed, an automated Checklist will be used to query you about testability features included in the design.
These questions are based on sound DFT principles derived from ASSET’s years of working with board designers to optimize boundary-scan test coverage. In addition, design practices specific to an engineering organization can be reflected in the Checklist in order to ensure consistency across all of a company’s designs.
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Next, the DFT Analyzer’s Design Validation tool will be launched after CAD (computer aided design) information has been compiled. CAD data is imported into DFT Analyzer so that the above-mentioned Design Validation tool can determine whether any pre-established DFT rules have been broken or overlooked. The tool recommends a remedy if it encounters a broken rule.
DFT Analyzer’s third tool, dubbed Test Coverage Analysis, will be engaged during the final stages of design, before first prototypes of a board are manufactured. The Test Coverage Analysis tool will determine the extent of boundary-scan test coverage when certain types of tests, such as interconnect or memory tests, are run on the board.
Eliminating Test Points
In addition, the report will contain information about which on-board test pads used by an ICT (in-circuit test) system can be eliminated by substituting a boundary-scan test for an ICT operation. Eliminating ICT test points can save board space and reduce the complexity and cost of an ICT test fixture. In addition, the Test Coverage Analysis module can output its results to the DFT Analyzer’s design browser. It graphically displays available test coverage in a schematic view.
The final output of DFT Analyzer will be a boundary-scan description of the design that can be imported directly into ASSET’s boundary-scan test generation tool in ScanWorks, the company’s JTAG system. With minimal additional effort, a set of boundary-scan tests can be optimized for first-prototype boards, and then re-used through the manufacturing process and into system test and field support.
Price And Availability
DFT Analyzer will be available during the first quarter of 2006. Limited-term licensing begins at $10,000. Standard and network licenses are also available, ensuring pricing options and low cost-of-ownership.
ASSET InterTech, Inc., 2201 North Central Expressway, Suite 105, Richardson, Texas 75080. Phone: 888-694-6250. Fax: 972-437-2826. E-mail: firstname.lastname@example.org
ASSET InterTech, 888-694-6250, www.asset-intertech.com