On 2 November 2005, Actel Corporation unveiled the new capabilities that are available with its Libero Integrated Design Environment (IDE). The new Libero 6.3 software provides a secure design flow – from synthesis through implementation – for integrating Actel's CoreMP7, the industry's first soft ARM7 family processor, into Actel's single-chip, nonvolatile field-programmable gate arrays (FPGAs).
With this software release, Actel builds on the capabilities of its SmartTime static timing analysis environment to deliver enhanced minimum-delay support, uniquely enabling precision hold-time characterization for high-speed FPGAs. The enhanced software also automates the task of I/O voltage assignment and supports Actel's new RTAX4000S devices, the industry's highest density FPGA for space applications.
Optimized to support CoreMP7
Libero 6.3 provides an advanced block-level methodology that enables designers to aggregate IP around CoreMP7, map it into Actel's ProASIC3/E FPGA fabric with predictable timing, and verify operation. Tight integration with industry-leading, third-party tools from Magma Design Automation, Mentor Graphics, and Synplicity enables seamless synthesis, verification, and physical synthesis for designs incorporating CoreMP7.
Enhanced black-box support from Synplicity and Magma Design Automation, within their respective synthesis and physical synthesis tools, enables a secure flow, while Actel's own proprietary tools provide state-of-the-art encryption to protect the valuable ARM7 IP from unauthorized access. Actel's tools also deliver the timing analysis and layout functionality necessary to simplify and accelerate system design using CoreMP7.
Unlike SRAM-based devices, Actel's impenetrable flash architecture and powerful encryption techniques safeguard ARM7 and user IP against reverse engineering or theft, helping to preserve a company's competitive advantage and protect its development investment. Delivering this unique, end-to-end secure flow for Actel devices, Libero 6.3 enables the first ARM processor-based technology for implementation on programmable logic as a soft IP core. As a result, designers can build cost-effective solutions for a variety of value-based consumer, industrial, automotive and high-reliability applications.
Advanced features and new device support
Libero 6.3 delivers enhanced timing and layout capabilities that promote better design practice and designer efficiency. Actel's SmartTime timing analysis environment now features "Enhanced_Min_Delay (EMD)" characterization, a comprehensive process that, for the first time, brings precise hold-time analysis to the realm of FPGA design. EMD eliminates the need to over-guardband a design for minimum delay, improving time-to-design closure. This significant enhancement uniquely enables SmartTime users with the benefit of a more comprehensive way to verify setup and hold timing at the internal and chip-to-chip level.
Libero 6.3 also employs advanced matching algorithms to automate I/O voltage assignments, alleviating the time-consuming process of optimizing I/O schemes for complex, processor-based designs. This new I/O bank assigner automatically assigns VCCI voltages and VREF pins to appropriate unassigned I/Os during layout. Automating this previously manual process simplifies FPGA design, especially for complex devices containing as many as 80 different types of I/Os.
Further, Libero 6.3 delivers the tools necessary to target, layout, and verify the next-generation of high-reliability space designs using Actel's new RTAX4000S device. At four million system gates, the RTAX4000S device is the industry's highest density radiation-tolerant FPGA.
Pricing and Availability
The Actel Libero 6.3 IDE is available in a Platinum edition for Windows and Unix platforms, which sell for $2495 and $4995 respectively. A free Gold edition is also available for Windows. All editions are one-year renewable licenses. More information is available at www.actel.com.