SAN FRANCISCO Programmable logic supplier Lattice Semiconductor Corp. and EDA company Synplicity Inc. jointly announced Tuesday (Nov. 29) that, as a result of an ongoing strategic relationship between the two companies, version 8.4 of Synplicity's Sinplify Pro logic synthesis engine provides additional performance enhancing features for Lattice FPGA devices, resulting in up to 20 percent performance improvement and significant area savings.
In a statement issued by the two companies, Jeff Garrison, Synplicity's director of FPGA products, said the performance improvement is the result of performance-enhancing features that have been added to version 8.4 of Synplify Pro. Garrison said the new features include pipelining, re-timing, automatic RAM inferencing and inferring sequential shift operations in the RTL for implementation in RAM.
"Performance improvement translates into more effective timing closure and lower cost solutions for our FPGA customers," said Tim Schnettler, director of design tools marketing at Lattice. "Synplicity is an industry leading provider of FPGA software and we believe our strengthened partnership will be a source of continual innovation and improvement for years to come."
Over the next two quarters, Lattice (Hillsboro, Ore.) and Synplicity (Sunnyvale, Calif.) plan to hold a seminar series detailing the performance benefits that can be achieved by using Synplicity's synthesis products with Lattice Semiconductor's FPGAs and complex programmable logic devices. The seminar series will include a technical discussion about the newest generation of Lattice FPGAs and ispLEVER design tools, as well as techniques for using Synplicity's Synplify Pro software to boost design performance, the companies said.
The seminar series will be held in cities throughout the U.S. through the rest of this year and in multiple cities in Europe and Asia in early 2006. More information about the seminar series is available on Lattice's Web site.