Lattice Semiconductor Corporation has announced its new ispClock second generation family of enhanced zero-delay clock generators, the ispClock5600A devices, along with the availability of the first device, the ispClock5620A. The programmable, E2CMOS-based ispClock5620 devices can generate up to 20 clock outputs, each with independently programmable output skew, I/O standard, and frequency selection. The non-volatile, in-system programmable ispClock5600A devices are pin compatible with Lattice's first generation ispClock5600 devices, but provide a number of additional features and parametric enhancements.
Heading the list of enhancements, the maximum VCO operating frequency of the ispClock5600A devices has been increased to 800 MHz. This supports the generation of popular clock frequencies such as 33.33MHz, 100 MHz, 133.33 MHz and 50 MHz simultaneously from a single master frequency. The input clock frequency range has been extended (5 MHz to 400 MHz) to enable support at 8.192 MHz, a popular telecom clock frequency. Additionally, the device's Universal Fan-out Buffer is able to source clocks to DDRII and QDRII memories (up to 400 MHz).
The ispClock5600A devices use seven on-chip counters (input, feedback and five for outputs) to provide fine granularity output frequency generation. The high-performance Universal Fan-out Buffer has a maximum pin-to-pin skew of 50ps, regardless of bank and frequency, while the maximum cycle-cycle (peak-peak) output jitter is less than 70ps, and the period jitter less than 12 ps (rms). The output skew of each clock net relative to the reference input can be further controlled in delay increments of 156 ps (lead or lag) to compensate for differences in circuit board clock network trace length. In addition, both the reference input and the Universal Fan-out Buffers can support a wide variety of popular single-ended and differential logic standards (LVCMOS, LVTTL, HSTL, SSTL, LVDS, LVPECL, Differential HSTL, Differential SSTL) at a variety of voltage levels. The input termination and output impedance of each output can be individually tuned to match each trace impedance, resulting in clock nets with high signal integrity.
The Lattice Windows-based design software, PAC-Designer Version 4.1, provides comprehensive design support for the ispClock5600A device family. In addition, utilities such as Graphical Skew Editor, Frequency Calculator and Frequency Synthesis support have been enhanced to address a wider range of application issues. Design configurations can be downloaded quickly into ispClock5600A devices via the PC parallel port. This version of the PAC-Designer software can be downloaded for free from www.latticesemi.com.
Pricing and availability
Prices for the first available device, the ispClock5620A, start at $6.80 in high volume (10KU+) quantities. The ispClock5620A, packaged in a 100-pin TQFP, is available immediately in both commercial (0C to +70C) and industrial (-40C to +85C) temperature grades. PACsystemCLK5620A evaluation kits also are available through authorized Lattice distributors or on the Lattice Web site for $295.
More information is available from www.latticesemi.com.