IDT introduced the industry's first off-the-shelf statistics engine that uses an integrated 64-bit arithmetic logic unit (ALU) to offload up to 800 additional data-path processor cycles (per 64-bit counter update), resulting in a 90% improvement in network processor cycles required for statistics computation. The result is increased packet processing line rate and deeper packet inspection to support new IP-based services.
The ALU coupled with the enhanced multi-port memory cell architecture allows the statistics engine to update multiple counters with an innovative "fire and forget" operation. This operation replaces the conventional Read/Modify/Write sequence, allowing the processor element to access and update as many as four counters on every clock cycle. The result is an up to 87 percent improvement in QDR-II bandwidth.
The statistics engine targets edge router, broadband access equipment and multi-service provisioning platforms, the statistics engine features a Network Processor Forum (NPF) Look Aside (LA-1) interface, and offloads such processor elements as NPUs, FPGAs and ASICs of the critical function of statistics tracking.
According to the company, there are other compute-intensive functions necessary to meet IP-based service requirements such as the transition from IPv4 to IPv6, and deployment of such content-rich services as streaming media and online gaming.
According to Michael Miller, IDT chief technology officer and vice president of the Systems Technology Group, "Customers looking to design a 10G (OC-192) edge/access/metro router, coupled with a current generation packet processor, will experience difficulty achieving line rates when supporting thousands of customer flows. This equipment requires differentiated services, and maintaining quality of service and service-level agreements at line rates with a single processor design is nearly impossible."
Miller goes on to say that by preventing the processor element from stalling on the restrictive external bus transactions, the IDT statistics engine will help customers overcome system-performance challenges.
Edge and access equipment tracks thousands of customer flows, well beyond the storage requirements of NPUs and ASICs, necessitating off-chip storage. At high speeds, stalling on multiple external multi-clock read cycles per packet for flow statistics is very costly. These stalls often require processor threads to context switch, adding to complexity and overhead.
The multi-port memory cell architecture of the statistics engine also ensures coherency for low latency statistics operations that require multiple statistics update every five nanoseconds, making it appropriate for 10G and above line rates. The configurable 64/32-bit ALU is also useful for systems upgrading legacy 32-bit operations to 64-bit operations without performance penalties.
Available in a 576-ball, RoHS-compliant flip-chip package, the product is currently sampling and priced at $55.00 to $65.00 in 25,000 unit quantities. For additional information on the IDT statistics engine, or to access a comprehensive white paper, visit IDT
Also see a Network Systems DesignLine exclusive article by IDT covering the use of statistics engines, Statistics engine reduces packet processor cycles 90%.