Santa Cruz, Calif. -- Chip designers are increasingly turning to multivoltage designs for power management, but tool support has been lacking. Startup ArchPro Design Automation Inc. plans to change that this week, rolling out capabilities to enable multivoltage equivalence checking and multivoltage synthesis.
Dividing a chip into multiple voltage islands is one of the most effective ways to reduce power consumption--and it's practically becoming a requirement at 65 nanometers (see Jan. 16, page 47). But "traditional synthesis or equivalency checking never considered the variation of voltage into its analysis," said Srikanth Jadcherla, ArchPro's founder and CTO.
ArchPro (Fremont, Calif.) this week will field MVRC, a multivoltage rule checker that runs with third-party equivalence checkers, and MVSYN, which automatically inserts level shifters and isolation gates into RTL netlists for synthesis. The products complement ArchPro's first product, MVSIM, which runs alongside HDL simulators to provide multivoltage support (see Aug. 15, 2005, page 28).
All three products use the same compilation front end, which allows designers to describe voltage islands and states. While it could be viewed as a proprietary language, it just looks like a form or a template to the user, Jadcherla said. The three products are independent; none requires use of the others to run.
MVRC serves two functions. By itself, it's a static rule checker; used with equivalence checkers such as Synopsys' Formality or Cadence Design Systems' Con- formal, it brings the impact of multiple voltage islands into the analysis.
As a rule checker, MVRC finds such problems as illegal crossovers and missing protection circuitry. It might detect missing or incorrect level shifters and isolation gates. It can also spot illegal states and transitions. Jadcherla said the rules are technology-independent and are simply aimed at finding "bad design cases."
When run with Formality or Conformal, MVRC essentially uses those products as client engines. While equivalence checkers give pass-or-fail information, MVRC can note what is passing or failing and correlate it back to states and voltages, thus verifying equivalency across all possible voltage combinations. The input to MVRC is RTL code or a gate-level netlist, along with the user's specification of islands and states.
MVSYN runs before RTL synthesis and automates a process that typically takes hundreds of scripts and months of hand coding, Jadcherla said. No scripting is necessary to support multiple voltage islands.
"If you write a script, you make it customized to the architecture, and if the architecture changes a little later you have to redo the whole effort. We can handle it as a pushbutton operation," Jadcherla said.
The capability is needed because HDL code doesn't perceive a difference between voltage islands or the transition of voltages and states, he said.
MVSYN also supports engineering change orders. If the user adds or deletes a power management state, the tool can figure out what needs to change in the RTL code or netlist. The input to MVSYN is RTL code with the user's voltage island and state specification. The output is modified RTL that can run in any synthesis tool.
The new ArchPro offerings are available now. The company did not release pricing information.