SAN FRANCISCO Claiming an industry first, programmable logic supplier Xilinx Inc. Monday (Jan. 31) announced the immediate availability of a Virtex-4 FPGA-based, 667 megabit-per-second DDR2 reference design. According to Xilinx, the reference design provides the highest bandwidth of any memory interface solution in the FPGA industry.
Xilinx (San Jose, Calif.) said the 667 DDR2-SDRAM interface uses Virtex-4 ChipSync technology, a run-time calibration circuit that the company says improves design margins and overall system reliability while reducing design cycles. Xilinx plans to showcase the new solution at DesignCon 2006, Feb. 6-9 in Santa Clara, Calif.
Xilinx said its memory solutions are verified in hardware using memory devices from industry leaders like Micron Technology and Samsung, including the new 667 Mbps DDR2 reference design, which can be downloaded from the Xilinx Web site.
According to Xilinx, ChipSync technology simplifies the implementation of memory interfaces by compensating for routing, process, temperature and voltage variations that produce skew between data and clock signals that may not be correctly estimated at design time. This feature alleviates post-design adjustments and improves design cycles and overall system reliability, Xilinx said.
Also Monday, Xilinx announced the availability of several reference designs that the company said could accelerate the development of complex image enhancement algorithms in high-quality flat-panel displays. Available through partners in the Xilinx Alliance Program, the reference designs are proven on a Spartan-3 based validation platform developed specifically to address key technical challenges faced by LCD and PDP television panel and video board designers, Xilinx said.
More information about the display reference designs is available on the company's Web site.