Lattice Semiconductor Corporation has announced its LatticeSC System Chip FPGA family, which is designed to provide the unsurpassed performance and connectivity essential for high-speed applications.
Fabricated on Fujitsu's 90nm CMOS process technology utilizing 300mm wafers, LatticeSC FPGAs are packed with features that accelerate chip-to-chip, chip-to-memory, high-speed serial, backplane, and network data path connectivity to provide "Extreme Performance."
Integrated into the LatticeSC devices are high-channel count SERDES blocks supporting 3.4 Gbps data rates, PURESPEED parallel I/O providing an industry-leading 2 Gbps speed, innovative clock management structures, FPGA logic operating at 500 MHz, dense block RAM, and Lattice's unique Masked Array for Cost Optimization (MACO) embedded structured ASIC blocks (Fig 1).
1. LaticeSC FPGAs feature MACO Structured ASIC blocks.
LatticeSC: High channel count SERDES + flexiPCS
Lattice FPSCs (Field Programmable System Chips) were the first programmable logic devices to combine SERDES and embedded Physical Coding Sublayer (PCS) blocks on an FPGA device. LatticeSC devices advance that pioneering concept by providing up to 32 SERDES channels, each running at data rates from 600 Mbps to 3.4 Gbps.
In order to support backplane applications in which the drive lengths approach 60 inches, designers can enable the Transmit Pre-emphasis and Receive Equalization features that are built into the SERDES. The LatticeSC SERDES also has an extremely low typical power consumption of 100 mW/channel @ 3.125 Gbps. Jitter specifications at 3.2 Gbps are 0.29 UI for total transmit jitter and 0.8 UI for total receive jitter tolerance. Other programmable features such as AC/DC coupling and half rate modes are also present to provide users with extraordinary flexibility in implementing their designs.
The flexiPCS block can be configured to support an array of popular data protocols, including PCI-Express, 1.02 or 2.04 Gbps Fibre Channel, Gigabit Ethernet (1000 BaseX), 10 Gigabit Ethernet (XAUI), Serial RapidIO, and SONET (STS-12/STS-12c, STS-48/STS-48c, and TFI-5 support at 10Gbps or above). The flexiPCS block features best-in-class Ethernet and PCI Express support, with embedded physical layer functionality for encoding/decoding, clock tolerance compensation, CRC generation/checking and multi-channel alignment.
Masked array for cost optimization (MACO)
Although they lack the flexibility of FPGAs, Structured ASICs have become more popular due to their density and performance. Unlike full-custom or standard cell ASICs, structured ASIC designs cost far less because they employ only a few masks for customization. Lattice embeds up to 12 structured ASIC blocks, called MACO blocks, within each LatticeSC FPGA. Each MACO block has approximately 50,000 usable ASIC gates that can be used to implement Intellectual Property (IP) cores requiring maximum performance together with minimum silicon area and low power dissipation. The MACO blocks also provide abundant routing connections to I/O pins, block RAM and programmable logic blocks.
Lattice plans to introduce a number of LatticeSC devices with pre-designed blocks covering a broad range of common applications that require high-speed connectivity. Pre-designed MACO-based IP will include Lattice's innovative flexiMAC multi-protocol communications engine supporting multi-layered protocols such as PCI Express and Ethernet, as well as SPI4.2 and high speed DRAM/SRAM Memory Controllers. Lattice will offer these standard MACO IP functions pre-programmed into special versions of its LatticeSC family, which is designated the M-series.
PURESPEED I/O: 2 Gbps extreme performance and connectivity
LatticeSC PURESPEED I/Os support a broad range of differential and single-ended I/O standards, including LVTTL, LVCMOS, SSTL, HSTL, GTL+, LVDS, LVPECL and Hypertransport. Each LatticeSC I/O pin includes an Input Delay (INDEL) alignment block with 144 taps at 40ps intervals. For high-speed source synchronous I/O, PURESPEED I/O technology features an Adaptive Input Logic (AIL) block for closed-loop pin timing monitoring and control. This feature dynamically maintains proper setup and hold time margins on a bit-by-bit basis. Using this feature, designs can accurately support speeds of up to 2 Gbps on a single pin.
LatticeSC FPGAs also provide dedicated "gearbox logic" for SDR, DDR1 and DDR2 interfaces. On-chip clock dividers support the clocking requirements of the gearbox logic, reducing the need to use generic PLL/DLL resources for this purpose.
Low power On Die Termination (ODT) is provided to minimize stub lengths, which improves performance. Dynamic switching of the termination is handled automatically on the device to support standards such as DDR2 memory.
500 MHz FPGA fabric and embedded block RAM
The LatticeSC device is manufactured on Fujitsu's 90nm CMOS process technology which, combined with an optimized logic block and ample routing, yields an FPGA fabric easily capable of 500MHz performance (e.g., 64-bit address decode). The basic logic element of the array is the Programmable Function Unit (PFU), which can be configured for logic, arithmetic and distributed RAM/ROM functions. PFUs are divided into four slices, each containing two 4-input SRAM Look-up Tables (LUTs) plus registers. Slices are individually configurable and can be cascaded, as can the PFUs for larger functions. Densities in the family span 15K to 115K LUTs.
LatticeSC devices offer 1 to 7.8 Mbit embedded block RAM (EBR) capable of 500HMz operation. Each 18Kb sysMEM EBR block can implement single port, true dual port and pseudo-dual port or FIFO memories. Dedicated FIFO support logic allows the LatticeSC devices to efficiently implement FIFOs without consuming LUTs or routing resources for flag generation.
The Lattice SC FPGA is also packed with hierarchical clocking resources and, unlike competitive devices, provides both PLL and DLL resources to deliver a no-compromise solution for clock management
1V Core Supply for Low Power Applications
The LatticeSC FPGA fabric features an industry-exclusive expanded operating range power supply core, supporting core Vcc power supplies of both 1.2V and 1V. Customers with very tight power budgets can use a 1V power supply to reduce core FPGA power dissipation by over 50%, while decreasing fabric performance by only 15%
FreedomChip cost reduction
For high volume applications, Lattice also announced plans for a cost-reduction path for its LatticeSC family. Customers can reduce the price of selected LatticeSC FPGA designs by up to 50% by converting to the pin compatible Lattice FreedomChip. Through automatic insertion of scan logic, the customer's netlist is utilized to produce low cost custom-tested silicon without the need for difficult back-end design conversion associated with traditional Structured ASICs. Further details on Lattice's FreedomChip technology will be announced during the first half of 2006.
Sample application for the LatticeSC FPGA
A typical application for the LatticeSC FPGA is a universal connectivity bridge in a multi-service networking system. A single LatticeSC device can support the various data streams used in today's networks. To handle traffic shaping, the LatticeSC device will seamlessly interface multiple 10G network processors using multiple SPI4.2 cores embedded in Structured ASIC blocks. High-speed memory interfaces are required to buffer these faster line rates and the LatticeSC supports all of the latest memory standards. To interface to a terabit switch fabric, the LatticeSC FPGA can drive a system backplane with up to 32 SERDES channels supporting a number of serial standards such as Serial RapidIO, SONET/SDH, PCI Express, Ethernet and Fibre Channel.
Design tools and IP support
Design support for LatticeSC devices is provided by the Lattice ispLEVER Version 5.1 Service Pack 2 design tool suite. The ispLEVER tools provide designers with access, in one software package, to all Lattice digital devices and include simulation and synthesis support from Mentor Graphics and Synplicity.
An extensive range of IP cores, particularly suited for high-volume applications, will be available from both Lattice and its IP partners. Complete details of IP support will be announced throughout 2006.
Availability and pricing
Prototypes of the first LatticeSC device, the LFSC25, are available now. Remaining devices in the family will be moved to production during 2006. The LFSC25 has 8 or 16 SERDES channels, depending on the package option, running at 600 Mbps to 3.4 Gbps. The FPGA fabric offers 25,000 PFUs, 1.92 Mbit embedded block RAM, and 6 MACO structured ASIC blocks. The LFSC25 will be offered in a 900-ball fine pitch BGA (fpBGA) and 1020-ball flip chip BGA. Projected pricing for the basic LFSC25 in the 900fpBGA package in quantities of 25,000 for shipment in 2007 is $49.
For more information, visit the Lattice Semiconductor website at www.latticesemi.com.