Hillsboro, Ore.Competing with programmable logic-device behemoths Xilinx and Altera hasn't been easy, but Lattice Semiconductor has developed two feature-rich product lines that it believes could help it garner market share.
The FPGA maker launched its 90-nm generation of its FPGA devices, introducing LatticeSC system chip FPGAs and LatticeECP2, its second-generation "Economy Plus" device. Both product lines will be manufactured on Fujitsu Ltd.'s 90-nm technology, using 300-mm silicon wafers at its facility in Mie, Japan. Production of both devices is expected to be available by mid-2006.
The LatticeSC devices will compete in the high-end arena with Xilinx's Virtex-4 and Altera's Stratix FPGAs. And LatticeECP2 will compete in the low cost/high volume arena against Cyclone and Spartan devices.
"Lattice is dropping firmly into the middle points of these markets, competing head-to-head very favorably with these pre-existing suppliers. And it's our objective to get meaningful market share in the coming years," said Stan Kopec, corporate vice president of marketing at Lattice.
Lattice plans to enter the playing field with devices that are not only lower cost, but offer features that are a cut above its competitors' devices.
"Lattice is coming in as the number three supplier, so we've got a lot of room to make up. We have to be better at a lower price," Kopec said.
A closer look at LatticeSC
When Lattice began architecting the SC product line, it looked at the physical layer, which consists of two portions: signal integrity and protocol-specific logic. These are commonly used functions that are used throughout high-end applications, such as networking, wireless, wireline and storage. Sitting above that, designers need a fast and dense FPGA with built-in low-latency RAM to do proprietary co-processing/bridging. Taking this into account, the company developed the SC product line that is designed with a high-performance FPGA fabric.
"We try to cover challenges individually, and the first thing is the SerDes. They will be as common as LVDS was in the last five years," said Shakeel Peera, strategic marketing manager at Lattice. "Increasingly every high-end application will need SerDes, so as a result, we embedded four to 32-channels of SerDes in the entire family with the industry's most versatile and feature-rich physical coding sub-layer."
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Each SerDes channel or block is capable of supporting data rates from 600-Mbits/s to 3.4-Gbits/s. The LatticeSC SerDes has low typical power consumption of 100-mW per channel at 3.125 Gbits/s. Jitter specifications at 3.2-Gbits/s are 0.29 UI for total transmit jitter and 0.8 UI for total receive jitter tolerance.
In terms of density, the LatticeSC devices range from 15-K to 115-K LUTs, which run at 500-MHz. All of the blocks can be configured as logic, RAM/ROM, ripple, mux, and shift register.
The FPGA fabric also consists of up to 7.8-Mbits of embedded memory blocks; an operating voltage of 1.0-V-1.2-V; logic operating at 500-MHz and eight analog PLLs and 12 DLLs per device.
It also employs the company's PureSpeed parallel I/O technology. With PureSpeed parallel I/O, 15 single-ended and sever differential buffer standards are supported with speeds up to 2-Gbits/s. It features dedicated source synchronous interface logic with built-in dynamic alignment capability, which is available on every pin.
Peera said that the speed of its parallel I/O, which runs at 2-Gbits/s compared with 1-Gbits/s of competitive parts, differentiates the product line. The high performance PureSpeed buffer supports multiple differential and single-ended I/O standards, including LVTTL, LVCMOS, SSTL, HSTL, GTL+, LVDS, LVPECL and Hypertransport. It also includes on-chip termination.
The LatticeSC FPGA supports many protocols, including PCI Express, Serial RapidIO, Ethernet, Fibre Channel, SONET/SDH and SPI4.2, as well as several memory standards such as DDR2, QDR2 and RLDRAM.
Peera also cited other industry firsts, including the addition of both PLLs and DLLs for clock management since most FPGA makers only provide one. PLLs filter jitter; DLLs track jitter. PLLs are usually used in applications in which the designer needs to drive high-frequency signals off-chip from the FPGA outward. The design needs a clock management source that has low jitter and high performance. DLLs are useful since they take up a small amount of real estate and are good at measuring incoming clocks, he explained.
LatticeSC has 20 clock management resources per FPGA, which he claims is the most flexible FPGA clocking scheme. He also discussed how Lattice addressed power management issues.
"We are the only 90-nm device that can run either a 1.2-V core or 1.0-v core voltage operation," Peera said. "The 1.2-V is what most customers would choose. People with tight timing budgets can go down to 1.0-V as well, saving them 50% in terms of core powerthis is an industry first."
In addition, each LatticeSC embeds up to 12 structured ASIC blocks called masked array for cost optimization (MACO). Each block has approximately 50,000 usable ASIC gates that can be used to implement IP cores. Lattice plans to introduce LatticeSC devices with pre-designed MACO-based IP, including its flexiMAC multi-protocol communications engine that supports multi-layered protocols such as PCIe and Ethernet. Those devices will be dubbed the M-series.
Prototypes of the first LatticeSC device, the LFSC25 are available now. The LFSC25 has 8 or 16 SerDes channels, depending on the package, running at 600-Mbits/s to 3.4-Gbits/s. The FPGA fabric offers 25,000 PFUs, 1.9-Mbit embedded block RAM, and six MACO structured ASIC blocks. In the 900 fine-pitch BGA package, the LFSC25 will cost $49 in quantities of 25,000 for shipment next year.
With its second-generation ECP devices, Lattice has increased the density 2X; reduced the price by 50%; increased the I/O speed by 50%; and boosted DSP performance 3X.
Compared with its first-generation, 130-nm FPGAs, the ECP2 family increases available logic density to 70K LUTs with pricing at less than $1 per 1K LUT, and boosts the number of 18 X 18 multipliers to 88. The family offers pre-engineered 400-Mbits/s DDR2 memory interface support, configuration bit stream encryption and dual-boot configuration support. The ECP2 devices also feature transparent field reconfiguration (TransFR) I/O to simplify field updates.
To support low-cost DSP applications, the ECP2 devices embed sysDSP blocks capable of implementing multiply, accumulate summation and pipelining functions. The devices can implement DSP functions up to 28,600 MMACs at prices below $.001 per MMAC.
The logic and routing fabric of the ECP2 devices have been optimized to support distributed memory (provided on 12.5% of LUTs) and registers (provided on 75% of LUTs) to the typical application set. As a result, high-performance logic can be implemented on the ECP2 devices.
The LatticeECP2 family will be offered in two versions, the standard LatticeECP2 and a memory enhanced (LatticeECP2M) version to be announced later in 2006. The LatticeECP2M devices will increase density to 100-K LUTs and enhance memory capacity to more than five million bits of RAM. Six device densities from 6-K to 70-K LUTs are planned for the LatticeECP2 family plus additional members of the LatticeECP2M family.
The LatticeECP2 devices will provide between 55-K and 1-Mbit of embedded memory through sysMEM Embedded Block RAM (EBR), twelve to eighty-eight 18x18 multipliers and 95 to 628 I/O pins. In addition, each device provides two delay locked Loops (DLLs) and from two to six phase locked loops (PLLs) for timing control. The parts will be available in a variety of low-cost TQFP, PQFP and fine pitch BGA packages and operate from 1.2-V power supplies.
Samples of the first ECP2 device, the ECP2-50, will be available this quarter. It will be offered in 484 and 672 ball fine pitch BGA packaging options. It will be priced at $23.95 each in 100,000-unit quantities for delivery in 2007.
"In all, we believe we've taken the next step in the low-cost FPGA market," Peera said.
Lattice Semiconductor Corp., 1-503-268-8000 www.latticesemi.com