ANALOG DEVICES’ HIGH-SPEED CONVERTERS SET NEW POWER EFFICIENCY BENCHMARK FOR COMMUNICATIONS APPLICATIONS
NORWOOD, MAAnalog Devices, Inc. is introducing a family of high-speed 10- and 12-bit analog-to-digital converters (ADCs) targeted for broadband communications and wireless infrastructure applications, such as cable modem termination systems, third and fourth generation microcell and picocell base stations, and fixed point-to-point radios, where low power consumption is required to accommodate smaller form factors, but high-quality conversion performance cannot be sacrificed. The flagship device is a 12-bit, 250 million samples per second (MSPS) ADC that cuts power consumption by more than 40 percent, is available in a package 20 percent smaller than competitive ADCs, and maintains superior signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) at high intermediate frequencies (IFs).
“The AD9230 is the only 12-bit, 250-MSPS ADC that has been able to bring power consumption below the 500 mW threshold, thus increasing power efficiency, decreasing system size and minimizing thermal management costs—attributes which are extremely important for today’s high-performance wireless and wired applications,” said Kevin Kattmann, product line director, High Speed Signal Processing Group. “The AD9230, used in the transmit path of picocell or microcell base stations to optimize power amplifier linearization, also facilitates more rapid system deployment by enabling smaller-sized end-systems. In cable termination systems, growing demand for digital cable services is placing greater emphasis on bandwidth, calling for low-power ADCs that allow higher channel density.”
The 12-bit, 250-MSPS AD9230 is the flagship device in a family of pin-compatible, low-power converters being introduced today. The device operates from a single 1.8 volt supply, dissipates only 425 mW of power and is capable of maintaining excellent SNR (65.5 dBfs) and SFDR (82 dBc) with a 70-MHz input. The AD9230 features an on-chip reference and track-and-hold, two parallel low-voltage differential signaling (LVDS) output modes (ANSI-644 and IEEE 1596.3 reduced range link) to ease the interface to FPGAs, and a double data rate (DDR) mode which halves the number of parallel outputs required. The DDR, combined with the IEEE 1596.3 reduced range link LVDS option, further reduces power consumption to 385 mW.
To maximize system performance, the AD9230 can be used with ADI’s AD8368, AD8369 and AD8370 radio frequency (RF) variable gain amplifiers. The family includes the 12-bit AD9230 offered in three speed grades (250 MSPS, 210 MSPS, 170 MSPS) and the 10-bit AD9211 also offered in three speed grades (250 MSPS, 200 MSPS, 170 MSPS).