Lattice Semiconductor Corporation has announced the immediate availability of several key ispLeverCORE Intellectual Property (IP) modules that are user configurable via its IPexpress design flow. The new IPexpress flow, included as a standard feature in Lattice's ispLEVER design tool suite, significantly reduces design time by allowing IP parameterization and timing analysis on the designer's desktop.
In addition, a new hardware evaluation capability minimizes design risk by allowing free trial use of the cores prior to the purchase of an IP core license. IPexpress-supported functions include DDR, Ethernet, FIR, FFT, PCI and Reed-Solomon encoder and decoder. Lattice intends to make several more IPexpress cores available throughout the year.
By configuring IP cores using the IPexpress flow, designers are able to simulate, place and route, generate netlists, and run static timing analysis with their own logic and selected core parameters – all in real-time. The IPexpress flow also supports a hardware evaluation capability that makes it possible to create versions of the IP core that operate in hardware for a limited period of time without requiring the purchase of an IP license.
Availability and pricing
IPexpress user configurable cores available for immediate download from the Lattice IP server (accessible through the ispLEVER IPexpress GUI window) include:
- DDR Controller
- Dynamic Block Reed-Solomon Encoder
- Dynamic Block Reed-Solomon Decoder
- FIR Compiler
- Soft Error Detection
- Tri-Speed Ethernet MAC
User Guides for these IP modules can be found on This Page on the Lattice website. Lattice's ispLEVER design software – providing support for all Lattice CPLDs and FPGAs, including IPexpress support – is priced at $695 suggested resale for a complete PC-based seat.