San Jose, Calif. Atmel Corp.’s new AP7000 family of 32-bit processors has been designed to integrate on a single chip virtually all the functionality required for multimedia systems that are deployed in cell phones, digital cameras, PDAs, automotive infotainment, set top boxes, and home entertainment systems, as well as network switches/routers and printers.
Based on the company’s 166 MHz AVR32 core, the AP7000 contains a vectored multiplier coprocessor, 32 KBytes on-chip SRAM, 16 KB instruction and 16 KB data caches, memory management unit, DMA for high speed peripherals, and peripheral DMA controller that allows data to be transferred between peripherals and memories without wasting processor cycles.
The AP7000 architecture has a multilayer, high speed bus architecture that increases performance by allowing multiple operations to take place in parallel. In addition, there are two peripheral bus bridges that allow different clock frequencies to be set for high- and low-speed peripherals. In a conventional bus structure, the bus clock is determined by the fastest peripheral, such that slower peripherals that could operate on a slower bus, draw unnecessary power. The AP7000 allows the dynamic configuration of the individual clock frequencies of these two bridges, as well as the frequency of the CPU’s internal clock and that of the bus matrix.
On-chip peripherals include a 16-bit stereo audio DAC, 2048x2048 pixel TFT/STN LCD controllers, 480 Mbps USB 2.0 with on chip transceivers (PHY), two 10/100 Ethernet MACs. Serial interfaces include RS232, USART, I2S, AC97, TWI/I2C, SPI, PS/2 and several synchronous serial modules (SSC) supporting most serial communication protocols.
The AP7000 also integrates USB2.0 High Speed (480Mbps) protocol with on-chip transceivers (PHY), thus eliminating completely the requirement for external USB controller. The AP7000 also integrate two 10/100Mbps Ethernet Media Access Control (MAC) blocks for full industry standard connectivity.
This high level of integration allows the deployment of software libraries and application code on a single platform, and provides better control of system integration, testing and time-to-market, according to Atmel. The AVR32 core executes C/C++ algorithms three times faster the most popular competing processor core, the company said.
The throughput of the AVR32 core allows applications to be executed at a much lower clock frequency than is required by other processors. Since power consumption is directly affected by the clock rate, low frequency operation results in an immediate and proportional reduction in power consumption. The AP7000’s dynamically controlled, multi-clock bus structure and SoC-level integration further reduce system power drain.
For example, streaming a 320x240 MPEG movie over the AP7000’s on-chip Ethernet MAC and decoding it at 30 frames per second requires a CPU clock of only 120 MHz and system bus clocks of only 60 MHz. The processor also simultaneously runs a full Linux operating system and drives a QVGA TFT LCD with these clock frequencies. Total AP7000 power consumption for this application is only 250 mW.
Dynamic frequency scaling algorithms are used to set the clocks in each of the four domains at the lowest possible frequency for the function it is performing. For example, when the application is inactive, but a data transfer is happening via Bluetooth or IrDA, clocks for the CPU, bus matrix and high speed bridge may be shut down while the clock for the slow speed bridge is maintained.
The AVR32 core was designed from the ground up as a low clock frequency, low power CPU with special emphasis on maximizing the use of computational resources with a seven stage pipeline and three parallel sub-pipelines that supports automatic data forwarding and out-of-order execution; single cycle load/store instructions with pointer arithmetic that reduces cycles required for load/store cycles by 75%, accurate branch prediction with zero-penalty branches and maximizing code density to reduce cache misses.
For details of the chip, see block diagram below.
See related image
Unlike multicore or two processor solutions, the AP7000 has a single development environment for straightforward debugging. The AVR32 Instruction Set Architecture (ISA) is specifically designed for high-level programming languages like C, C++ and Java. Compilers with C, and C++ support include GNU GCC and IAR Systems’ Embedded Workbench. The compilers are able to utilize the AVR32 architecture’s SIMD- and DSP instructions from within the C/C++ programming environment. The IAR compiler is optimized to recognize patterns in the C-code that can use SIMD DSP instructions, thus further increasing the ease of use and performance when running compiled C-code applications. Both compilers support access to inline assembly for tight-loop / inner-loop algorithmic optimizations. GCC and GNU Debugger (GDB) are available directly from Atmel and plug directly into many Integrated Development Environments, including the Eclipse debug environment.
The AP7000 has a fully supported Linux 2.6 kernel to further ease the transition of existing code or the adoption of the many hundreds of thousands of open source and freely available applications available for use in embedded systems. Debug with trace capability us supported by Atmel’s JTAGICE mkII ICE.
The first AP7000 AT32AP7000 is available now in a 256 ball BGA package and is priced at $17 in quantities of 10,000. Additional AP7000 processors, priced from $8 to $17 (or lower), will be introduced during 2006.
Atmel's AVR32 product information may be retrieved at www.atmel.com/avr.
Atmel Corp. (408) 441-0311