Lattice Semiconductor Corporation has announced the immediate availability of its ispLEVER 6.0 programmable logic design tool suite. Fully supporting the newest 90nm LatticeECP2 High-Performance, Low Cost and LatticeSC Extreme Performance System Chip FPGA families, ispLEVER 6.0 boasts high performance and significant design flow enhancements.
Key highlights of the ispLEVER 6.0 release include support for the industry's fastest 90nm FPGAs, the introduction of a new, highly integrated Design Planner interface, improved support for schematic FPGA design and an expanded library of IPexpress user-configurable IP cores.
New design planner integrates preference editor and floorplanner
Lattice's new Design Planner integrates the two most used optimization tools, Preference Editor and Floorplanner, to more closely mirror the thought process and work flow of expert FPGA designers. Now users can move seamlessly from one task to another without unnecessary intermediate steps. The Preference Editor is used to define design parameters such as critical paths and timing objectives, which, because they are by definition device-specific, cannot be specified at the Hardware Description Language (HDL) level. The Floorplanner supports detailed control of logic placement within a device. Integrating these two interrelated tools greatly simplifies tasks such as assigning customized logic to physical device I/O pins. With this new approach, designers have a unified tool that helps them work seamlessly to complete these design tasks more quickly and efficiently.
The new IPexpress flow will significantly reduce design time by allowing IP parameterization and timing analysis on the designer's desktop. By configuring IP cores using the IPexpress flow, designers are able to simulate, place and route, generate netlists and run static timing analysis with their own logic and selected core parameters in real-time. In addition, a new hardware evaluation capability minimizes design risk by allowing free trial use of the cores prior to the purchase of an IP core license. IPexpress-supported functions include DDR, Ethernet, FIR, FFT, PCI and Reed-Solomon encoder and decoder. Lattice intends to make several more IPexpress cores available throughout the year.
Industry-leading synthesis and simulation
Lattice continues to work closely with third party synthesis and simulation partners Mentor Graphics and Synplicity to provide designers with industry-leading solutions as a standard ispLEVER feature. All third-party tools have been updated with performance enhancements for Lattice FPGAs. Included in the ispLEVER design suite are Mentor Graphics' Precision RTL synthesis version 2005c and ModelSim simulator version 6.1d, and Synplicity's Synplify synthesis version 8.5d.
New schematic design library for lattice FPGAs
The most efficient way for many designers to visualize and implement designs is through a schematic interface. In ispLEVER 6.0, a new schematic design library for the ispLEVER Schematic Editor allows designers to develop gate-level circuits based on library elements from the ispLEVER FPGA Libraries Help System. The libraries contain standard Boolean gates, latches, flip-flops and I/O buffers compatible across all Lattice FPGA device families. A new tutorial included in ispLEVER 6.0 provides design examples using a mixture of gate-level schematics modules generated by IPexpress, and RTL blocks to complete a design with the Schematic Editor.
The new Lattice FPGA schematic library supports the LatticeECP2, LatticeECP/LatticeEC, LatticeSC, LatticeXP and MachXO families.
Additional enhancements to ispLEVER design tools include:
- Design preferences can be viewed during place and route operation.
- Updated HTML reporting structure, format and information.
- New ispLeverDSP Block sets for use with MATLAB/Simulink design tools.
- Updated simulation libraries for use with Aldec Riviera and Active-HDL tools.
- Enhancements to the ispLEVER text editor.
- New manuals and tutorials that cover DSP design, IPexpress flow and FPGA schematic design.
A complete list of these and other new features and enhancements to the ispLEVER 6.0 design tool suite can be viewed at www.latticesemi.com/software.
Pricing and availability
The ispLEVER 6.0 software for Windows, supporting all Lattice digital programmable logic families, is priced at an industry best value of $695 and is available immediately. UNIX and Linux versions also are available.