Xpedion Design Systems announced what it says is the industry's first transistor-level phase-locked loop (PLL) solution for verifying complete closed loop noise and jitter. This allows PLL designers to fully verify their designs prior to silicon to save design spins and reduce time to production.
Phase-locked loops are present in a majority of complex integrated circuits produced today in applications ranging from microprocessors to wireless communications. They also represent one of the most challenging design hurdles to overcome and are often the reason for failing silicon. Xpedion has developed this technology in conjunction with close partners and has validated through measured silicon.
"We worked with Xpedion to successfully verify simulated results against measured data for our CMOS PLL with over 500 transistors operating at 622 Mhz, including the crystal oscillator and the integer divider," states Pierre Guebels, Vice President of Engineering at Phaselink Corporation. "This capability is a tremendous step forward in successfully verifying PLLs prior to tape-out."
This capability takes advantage of Xpedion's leadership in harmonic-balance capacity, simulation speed and phase-noise analysis. GoldenGate allows designers to view full noise contributions from all contributors, including the crystal oscillator, allowing designers to pinpoint and fix problems. Historically, this is done through an iterative process of respins.
"We are able to address a clear need in the industry to verify proper PLL operation through our advanced capabilities," says George Estep, Director of Applications Engineering at Xpedion. "This capability will save our customers painful design iterations allowing them to get their products to market faster."