By Eric Flink and Gidget Cathcart, Agilent Technologies, Plao Alto, Calif.
A design verification team developed a custom logic analysis program to test a complex switch-control system. A buffered digital I/O module, plugged into a multi-function switch/measure unit, provided capture, trigger, and playback features necessary to implement the test.
The completed application was later modifiedwith minimal effortto use a compatible digital I/O module compliant with the LXI (LAN eXtensions for Instrumentation) standard.
An engineering team faced the challenge of verifying the correct operation of an SCS (switch-control system). The SCS provides control signals to operate a number of general-purpose switches under programmatic control.
The SCS can deliver drive pulses ranging from 1-ms to 255-ms in width. The SCS specification calls for the pulse width to be no more than 1-ms longer than the specified pulse width, ensuring that the delivered power doesn't exceed the value required to operate a particular switch.
The switches may vary significantly in the power required for actuation. The power supply may be able to provide enough power to simultaneously operate multiple switches. The SCS enables the user to specify the maximum overlap.
As an example, suppose that the SCS has four switches configured with different pulse widths (t1, t2, t3, and t4). Assume that the power supply can drive no more than two switches concurrently. If you tell the SCS to close switches 1, 2, and 3, then the resulting pulse patterns on the control lines would resemble those in the figure.
Note that switches 1 and 2 are pulsed in parallel, but that the pulse for switch 3 can't start before either switch 1 or 2 completes.
Some switches provide verification signals that indicate switch position. The SCS can detect these signals and report an error when a switch fails to verify that it's in the expected position. Because the switches are mechanical devices, the SCS must wait for a period of time to allow for the switch actuation as specified by the switch manufacturer.
For example, the figure shows a switch closing with a pulse time of t1 and an actuation time of a1. By the end of period a1, the switch must assert its verification line or else the SCS will report a failure.
Testing The SCS
The SCS provides a rich set of capabilities that can control a variety of switches. Each of these capabilities must be verified by the test system, which must be able to measure four conditions:
* Delivery of drive pulses to the proper channels for durations within a tolerance of 1-ms
* Absence of any drive signals to any switches that should be idle
* Maximum number of overlapping pulses
* Detection of switch verification errors
The SCS test system requires the ability to simultaneously capture all signals being sent from the SCS to all switches, and do this at a resolution high enough to accurately determine pulse width. To exercise the SCS error-detection feature, the test system must also have the ability to simulate switch-verification signals.
The test system was designed using a multi-function switch/measure unit, a 64-bit digital I/O module, and a terminal card.1
With a maximum frequency of 10-MHz, the digital I/O module can capture pulse data and deliver verification signals with sufficient accuracy to test SCS timing tolerances. The buffered memory of the module permits the test system to capture long sequences of control pulses from the SCS, and also play back verification signals to the SCS. The module's pattern-matching and triggering features enable the system to accurately control the delivery of verification signals back to the SCS.
The figure shows the conceptual diagram for the test system. In the digital I/O module, four bytes (Bank 1) read the control pulses coming from the SCS (one bit assigned to each of 32 switch-control lines) and four bytes (Bank 2) provide verification signals back to the SCS.
Bank 1 is configured to read four bytes of input at a frequency high enough to ensure acquisition of multiple samples during each 1-ms control pulse. Each byte of the input buffer represents the instantaneous state of eight drive lines from the SCS.
The test controller in the figure starts a buffered read and then initiates a series of operations on the SCS.
The next figure represents the sampling of the drive lines from four switches. Each bit in the captured data buffer represents a binary state representation of a drive line.
The resulting data buffer can then be analyzed to determine whether the SCS delivered the pulses as expected. The maximum width is found by adding the bits in any sample (LWORD, below), and the width of each pulse is determined from the number of consecutive ones.
The SCPI (Standard Commands For Programmable Instruments) commands that configure the "digital read" in the above figure are given below:
Source:Mod:Clock:State OFF, 6
Source:Mod:Clock:Frequency 5000, 6
Source:Mod:Clock:Level 5, 6
Sense:Digital:Memory:Enable OFF, (@6101)
Configure:Digital:Width LWORD, (@6101)
Configure:Digital:Direction INPUT, (@6101)
Configure:Digital:Handshake SYNC, 2.5, 5, NORM, (@6101)
Sense:Digital:Threshold 2.5, (@6101)
Configure:Digital:Handshake:Sync:Strobe:Source EXT, (@6101)
Sense:Digital:Memory:Sample:Count 32000, (@6101)
Sense:Digital:Memory:Enable ON, (@6101)
Source:Mod:Clock:State ON, 6
This code segment refers to a digital I/O module installed in Slot 6 of the switch/measure unit (@6101); the module's clock output is connected to the Bank 1 handshake line.
The command sequence begins by disabling the clock's initial condition and then configuring it to run at 5-kHz with a 5-V output.
The digital I/O bank is configured for a 32-bit-wide input, and the strobe source is set to "external" (the clock output provides this signal). The memory is then cleared and the digital capture started. Finally, the clock is enabled, causing the digital I/O to begin sampling at 5-kHz.
At the end of the digital capture process, the data is retrieved using the following commands:
Digital:Memory:Enable OFF, (@6101)
To exercise the SCS timing with switch verification, Bank 2 of the digital I/O module is configured as an output buffer pattern generator. The output buffer contains a bit pattern that represents the verification signal for one of the switches.
The module's input buffer is configured with pattern matching enabled and a mask that is set to trigger when one particular drive pulse is asserted by the SCS. When the start of the drive pulse is detected, the output buffer plays back the verification buffer at the same sample rate. This is accomplished by connecting the Bank 1 and Bank 2 pattern interrupt lines and configuring them both with the desired signal conditions.
As shown in the next figure, the test system can deliver a verification signal at a precise time after the pulse. If the "verify" signal is delivered too late (or not at all) the SCS will flag the error. If the signal arrives just in time, the SCS will operate as expected with no errors.
The SCPI code below configures an input-pattern match on Bank 1 to detect a particular bit and, if that bit is detected, triggers the interrupt line:
Calculate:Compare:Data:Lword #hffffffff, (@6101)
Calculate:Compare:Mask:Lword #h00000001, (@6101)
Calculate:Compare:Type EQUAL, (@6101)
Sense:Digital:Interrupt:Mode COMPARE, (@6101)
The code sets up a comparison pattern of all ones and creates a mask that isolates a single bit in the input stream. The interrupt is configured to be asserted when there is a match with the defined pattern and mask.
Recall that the Bank 1 and Bank 2 interrupt lines are tied together and that the handshake clock source is delivered and controlled by on board clock. The following code segment sets up Bank 2 to output a pattern (initially all zeros followed by a single "on" bit) upon assertion of the interrupt line:
Source:Digital:Data:Lword 0, (@6201)
Configure:Digital:Handshake SYNC, 2.5, 5.0, NORM, (@6201)
Configure:Digital:Handshake:Sync:Strobe:Source EXT, (@6201)
Source:Digital:Level 5, (@6201)
Source:Digital:Memory:Enable OFF, (@6201)
Source:Digital:Interrupt:Mode START, (@6201)
Trace:Data:Digital:Lword (@6201), MyTrace, 0, 0, 0, 0, 0, 1, 1, 1, 1…
Source:Digital:Memory:Trace MyTrace, (@6201)
Source:Digital:Memory:Enable ON, (@6201)
This code segment first establishes the width and handshaking parameters. Next, memory is disabled and configured to start on receipt of an interrupt. A data trace is created and assigned to the channel and, finally, memory is enabled and then waits for the trigger response.
Porting To LXI
The organization created a new 64-bit digital I/O device compliant with the LXI standard.2
Viewed from any software application, the new device looks and operates just like the multi-function switch/measure unit with a digital I/O module installed in Slot 1.
Because the new LXI device is hardware-compatible and software-compatible with the original I/O module, migrating the SCS test system took minimal effort and time, requiring only a change in slot-address references (i.e., from (@6101) to (@1101) and (@6201) to (@1201)).
DIGITAL READ WITH PATTERN COMPARE ON BANK 1
Calculate:Compare:Data:Lword #hffffffff, (@1101)
Calculate:Compare:Mask:Lword #h00000001, (@1101)
Calculate:Compare:Type EQUAL, (@1101)
Sense:Digital:Interrupt:Mode COMPARE, (@1101)
Source:Mod:Clock:State OFF, 1
Source:Mod:Clock:Frequency 5000, 1
Source:Mod:Clock:Level 5, 1
Sense:Digital:Memory:Enable OFF, (@1101)
Configure:Digital:Width LWORD, (@1101)
Configure:Digital:Direction INPUT, (@1101)
Configure:Digital:Handshake SYNC, 2.5, 5, NORM, (@1101)
Sense:Digital:Threshhold 2.5, (@1101)
Configure:Digital:Handshake:Sync:Strobe:Source EXT, (@1101)
Sense:Digital:Memory:Sample:Count 32000, (@1101)
Sense:Digital:Memory:Enable ON, (@1101)
Source:Mod:Clock:State ON, 1
DIGITAL SWITCH VERIFICATION SIGNALS BANK 2
Source:Digital:Data:Lword 0, (@1201)
Configure:Digital:Handshake SYNC, 2.5, 5.0, NORM, (@1201)
Configure:Digital:Handshake:Sync:Strobe:Source EXT, (@1201)
Source:Digital:Level 5, (@1201)
Source:Digital:Memory:Enable OFF, (@1201)
Source:Digital:Interrupt:Mode START, (@1201)
Trace:Data:Digital:Lword (@1201), MyTrace, 0, 0, 0, 0, 0, 1, 1, 1, 1…
Source:Digital:Memory:Trace MyTrace, (@1201)
Source:Digital:Memory:Enable ON, (@1201)
RETRIEVING CAPTURED DIGITAL DATA ON BANK 1
Digital:Memory:Enable OFF, (@1101)
Since the 64-bit digital I/O module has the same digital hardware as the multi-function switch/measure unit module, the performance of the two systems are identical giving reliable, repeatable results, as the original SCS test system minimizing the time and cost in the system conversion.
The rich feature sets of the multi-function switch/measure unit and the 64-bit digital I/O module enabled rapid development of the SCS test system. The high degree of compatibility of the new LXI-based device made it simple to port the SCS test system platform to a smaller subsystem, requiring changes to only the slot-address references in the system software.
About The Authors
Gidget Cathcart holds a Bachelor of Engineering with Electrical Emphasis degree from New Mexico Highlands University, Las Vegas, NM. She has been with Agilent Technologies (formerly Hewlett-Packard) since 1995 in various roles, including test development design engineer for probing technology, package designer for ceramic ICs and, currently, digital hardware design engineer in Agilent's System Products Division.
Eric Flink holds a degree in computer science from the University of Kansas. He has been with Agilent Technologies since 1983 in various positions, including project manager for communication system test products and program manager for HP-UX workstation products. His current assignment is architecting and developing tools that enhance the value of Agilent’s general-purpose instruments.
1 - Agilent 34980A multi-function switch/measure unit, and 34950A 64-bit digital I/O module, and 34950T terminal card
2 - Agilent L4450A 64-bit digital I/O LXI module