Santa Cruz, Calif. -- Shiv Tasker, CEO of Bluespec Inc., says he's on a mission to reduce the cost of IC design by an order of magnitude. Bluespec will take a step in that direction this week with the release of electronic system-level synthesis support for SystemC.
Bluespec currently offers ESL synthesis from SystemVerilog design assertions. Unlike most other high-level synthesis providers, however, Bluespec targets control logic design. Now the company is claiming to bring SystemC synthesis to complex control logic as well as to data paths, and in a different way from previous offerings.
"Other SystemC products fall into the category of algorithmic synthesis, with loop unrolling and so forth," said Tasker. "We handle the rest of the system on-chip. What we bring to the table is an ability to extract concurrency." As a result, Tasker said, design and verification for an IC should take only half the time it would otherwise take.
Bluespec is offering the first ESL control logic synthesizer, said Gary Smith, chief EDA analyst at Gartner Dataquest. "They do have their proprietary aspects, but they are still getting a lot of attention," Smith said. "They really don't do algorithmic synthesis, which is what all the other ESL synthesizers are doing."
To make its synthesis possible, Bluespec is introducing ESL synthesis extensions (ESE) for SystemC. ESE adds two key enhancements to facilitate concurrency and communication: atomic transactions, or rules, and automated formal interface methods.
"Modeling concurrency today in SystemC is based on threads and events, which is really a low level of dealing with complex concurrency," Tasker said. "We abstract that and bring a tremendous value-add."
ESE is implemented in a header file that anybody can read, said Elliot Mednick, a Bluespec developer. This file, he said, provides extensions in a manner similar to the Open SystemC Initiative (OSCI) transaction-level modeling extensions. ESE also comes with a library. "We have our own scheduler, which replaces the use of threads in a model, and we handle concurrency and atomicity a little differently," he said.
Any tool that can support the OSCI SystemC simulator can run ESE models, Mednick noted. A user can write a conventional SystemC model with threads and link it with ESE. Mednick said Bluespec is currently talking to OSCI about the extensions, and hopes they will become an OSCI standard.
According to Bluespec, there are a number of problems with thread-based solutions. Acquiring and releasing multiple resources for a transaction is messy and error-prone, and it's hard to avoid deadlock and livelock, according to the company. ESE rules are said to express multiple-resource transactions simply, correctly and efficiently, and to provide synthesizable code.
ESE's formalized interface method calls, or "contracts," also help, Tasker said. "When you are writing a SystemC model with threads and events, you are responsible for scheduling and detecting locks and interlocks across module boundaries," he said. "Here, we will detect and schedule appropriately anytime you use these method calls across a module."
ESE supports both untimed and clock-scheduled models, but synthesis generally requires the latter. "The algorithmic synthesis guys can take in a constraint file and an untimed algorithm, and figure out a clock for you," Tasker said. "We don't do that. We say, give us the clock, and we will cram as much concurrency into each clock cycle as your design permits."
One thing that's different about the Bluespec approach, he noted, is that "the microarchitecture is under the control of the engineer. The engineer specifies all state elements. We don't invent architecture."
A free implementation of Bluespec ESE is available today at www. blue-spec.com. The free version supports language extensions for untimed simulations with the OSCI SystemC simulator. ESE Pro, a version that is for sale, adds support for clock-scheduled simulations as well as untimed simulations.
In the absence of a synthesis tool, which will come later, ESE can be used for hardware/software co-design, Tasker said. The company claims that ESE helps verification engineers express complex, concurrent activities, and provides a single environment for architectural exploration and design implementation.
ESEComp, to be rolled out later this year, will synthesize ESE SystemC designs into Verilog RTL code. Bluespec is hoping to demonstrate it at this July's Design Automation Conference, Tasker said.
The tool is said to serve all design styles and to be most useful for complex control logic or complex data paths. As for quality of results, "we have not seen anything that's worse than hand-coded RTL," Tasker said.
"I have a personal vision--I want to bring the cost of developing a chip down by a factor of 10," Tasker said. "If it costs $20 million to $30 million to get a chip out, I'd like to see it get down to $2 million to $3 million over the next five years. That involves improving the whole interaction between hardware and software. And that's why we're taking this [ESE] approach."
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