Sunnyvale, Calif. -- New tools from Altera Corp. give system designers the ability to trade off performance and power while delivering some of the densest FPGAs ever seen, company officials say.
The result of extensive study and interaction with customers, the improved tools are aimed at Altera's upcoming Stratix III line, due by year's end. Altera previewed the tools for EE Times last week. At the same time, it showed an enhanced version of its adaptive logic module (ALM) for 65-nanometer FPGAs.
The ALM, introduced several years ago when Altera unveiled its Stratix II FPGAs, is key to the flexibility of the Stratix II and III series, since it lets designers implement various combinations of lookup-table logic configurations in each module.
Giving customers what they want is the mark of any market-savvy company, but customer demands are often at odds with what vendors can deliver. In field-programmable gate arrays, for example, customers want higher density and performance at lower power levels, characteristics generally seen as contradictory. In the real world, power consumption typically increases as performance rises or more gates are integrated on a chip. Vendors must usually give up on at least one of the three characteristics to deliver products that come close to meeting customer requirements.
Balancing those factors remains a key differentiator between Altera and its closest competitor, Xilinx. A continuing debate will consider whether the ALM or Xilinx's 6-input lookup-table approach in its just-released Virtex 5 line (see page 1, May 15) is the more-efficient approach for the basic logic building block, said Paul Ekas, senior product marketing manager for high-density FPGA products at Altera. The ALM's flexibility allows designers to pack multiple lookup tables (LUTs) into a single ALM, Ekas said, citing density experiments that showed two tables can be configured into a single ALM about 80 percent of the time.
"Furthermore, about 40 percent of the time two 4-input LUTs can fit in an ALM, and about 24 percent of the time two 5-input LUTs can fit in a single ALM." Ekas calls Xilinx's 6-input LUT less-flexible. "Although it has the ability to pack two 5-input LUTs in one 6-input element, he said, "the LUT must share many inputs and thus the packing will rarely happen." Ekas also estimates that 63 percent of the time, the 6-input LUT will not be fully used.
In addition to their logic flexibility, the enhanced ALMs developed for the Stratix III line incorporate software-configurable features so designers can select various power and performance characteristics. That will let designers better optimize the system logic performance of functions configured in the FPGAs, said Robert Blake, Altera's vice president of product planning. But the solution, he said, is not just improved silicon. An enhanced version of the PowerAware software will give designers the ability to set various constraints and work through the synthesis, place and route and assembler to arrive at a power-optimized design, Blake said.
As with most CMOS technologies, the design approach for the Stratix III family will let designers trade off power vs. performance. And the 65-nm process technology will deliver FPGAs with many more gates and much higher performance than the current Stratix II line. At the same time it will lower the power consumed per gate (see figure above). For example, a Stratix III device running 20 percent faster than a Stratix II will consume 30 percent less power; if clocked at the same speed as Stratix II chips, Stratix III devices can trim power consumption by 50 percent. And if speed is not the main concern and the Stratix III chips are clocked at speeds 30 percent lower than a Stratix II device, as much as 70 percent of the total power can be saved.
The combination of 65-nm process technology and configurable power in each ALM helps drive down overall power in the Stratix III line. The programmable power technology helps reduce both static and dynamic power. Similarly, silicon process optimizations will also reduce both static and dynamic power. Additional features such as the ability to power down unused circuits on the chips will help to further reduce static power consumption, while the enhanced PowerPlay power optimization algorithms in the next release of Altera's Quartus II design software, combined with the ALM power configuration capability will help lower the dynamic power consumption.
The next Quartus II release will include support for design-space convergence that combines power, performance and area constraints. Enhanced power estimation and timing analysis tools will support more-rigorous constraints tied to 65-nm process technology, and enhanced place and route algorithms will enable localization of logic nets so they can toggle at higher speeds. An enhanced assembler will program unused circuitry on the chips to power down to minimize the static power drain. These features are in addition to tools already available in version 6.0 of the Quartus II tool suite (see May 8, page 40).