San Jose, Calif.Just six weeks after the Virtex-5 FPGA launch, Xilinx Inc. has made available the Integrated Software Environment (ISE) 8.2i tool suite that is tailored to support its 65-nm devices.
Like the versions that came before it, ISE 8.2i is being touted as the complete design product to enhance performance, productivity and power of Xilinx's FPGAs. The latest edition supporting the Virtex-5 family delivers an average of 30% faster performance, which translates into a two speed-grade increase compared to its previous tool suite release targeting the Virtex-4 platform, according to Mark Gusman, product marketing manager based in Longmont, Colo.
"That two-speed grade in addition to performance also talks to reduce costs by being able to target lower devices and talks to quicker time-to-market so that designers are able to achieve their goals earlier in the design process," he said.
The majority of the performance boost is a direct result of the enabling features within the Virtex-5 silicon architecture, he added. However, ISE 8.2i has been enhanced with several performance and productivity features.
ISE 8.2i builds on Fmax technology, which was introduced with the ISE 8.1i environment to enable what the company claims is the industry's fastest logic performance. For more on Fmax, click here: www.xilinx.com/ise/fmax/. The 8.2i tool suite features next-generation physical synthesis with critical pre- and post-routing optimization for Virtex-5 designs.
ExpressFabric technology offers enhanced routing support, which reduces levels of logic and signal delay while packing designs more efficiently. Virtex-5 is the first family of FPGAs to employ the ExpressFabric architecture, which delivers 6-input Look-up Tables (LUT). ExpressFabric technology allows the user to configure LUTs as either 6-input or dual-output 5-input generators. For more information on ExpressFabric, click here: www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/ExpressFabric.htm.
"The 6-input LUTthat was a big jump to the software. How we take advantage of the low-level architecture is core to the translation, mapping and place and route," Gusman said. For example, when comparing 64-bits of RAM between a 4-input LUT on the Virtex-4 with a real 6-input LUT on a Virtex-5, the user is able to fit more logic into a smaller area. That translates into a 60% improvement on the logic that can be packed into the Virtex-5 architecture, he added.
With the ExpressFabric architecture, the designer can fit wider functions and distributed memory into fewer LUTs, resulting in less routing resources and fewer levels of logic. Diagonally symmetric interconnect routing minimizes hops, which reduces the signal delay from Configurable Logic Block (CLB) to CLB to improve performance.
The tools don't have to work quite as hard to place certain blocks of logic to achieve timing goal.
"It's continued efficiency in the routing as we get into newer and newer architectures," said Lee Hansen, senior product marketing manager at Xilinx.
ISE 8.2i also delivers a new interactive timing closure technology that designed to provide tighter correlation between logical and physical design domains. What Xilinx has done is taken the first steps towards building an environment where the user has easy access to tools (floor planner, constraint editor, timing analyzer and PACE) by integrating them within the ISE design environment.
"It's building a cockpit environment so that the user isn't going and out and searching for individual tools, but they are all there at the click of a mouse," Gusman said. "The tight integration of plug-in tools allows much more intuitive, much easier and much faster design exploration."
Like its predecessor, ISE 8.2i also includes Xplorer, which is a utility that helps users find the best design results through multiple implementation runs using different place and route settings and constraints. With ISE 8.2i, users have the ability to run up to 20 implementations of the design and save the best results into the ISE project.
"With the benchmarks we're using internally, we're seeing a 10% better improvement on the design where we go ahead and throw a bunch of iterations using these different options in an automated fashion," Gusman said.
ISE 8.2i also features Xpower Estimator tool. With Virtex-5, Xilinx has gone through extensive characterization to build a suite of tools that allows the user to better explore power usage within their design. Xpower enables designers to specify the power parameters of their design and look at the power variance in several ways. The power estimation spreadsheet is separate from the ISE design tool; users don't need a license to access it. Xpower is available as a free download at www.xilinx.com/power.
The ISE 8.2i design suite is accompanied by the release of the ChipScope Pro 8.2 debug and verification software. Available as an add-on option, the ChipScope Pro 8.2 product reduces verification cycles by up to 50%. Also included is the newest release of the ChipScope Pro Serial IO Toolkit, providing simplified debugging of high-speed serial IO designs for Virtex-4 FX FPGAs.
All versions of ISE 8.2i software packages support Windows 2000 and Windows XP and Linux Red Hat Enterprise 3.0. ISE Foundation also supports Solaris 2.8 and 2.9.
ISE 8.2i Foundation and ChipScope Pro 8.2 configurations are immediately available with prices ranging from $695 to $2495. Full-featured 60-day evaluation versions can be downloaded from the Xilinx web site at no charge. For more information about the ISE 8.2i software suite, visit www.xilinx.com/ISE.
Xilinx Inc., 1-408-559-7778, www.xilinx.com