LONDON Fabless semiconductor startup MnD Semiconductors has developed a chip architecture that can be easily scaled from low cost, high definition, video decoders to high performance, real time, multi-channel, video encoders and transcoders.
The company, which is based near Paris, France, will launch a chip dubbed Silver Screen based on the technology at the IBC congresss, which starts September 8 in Amsterdam.
The company says the architecture is fully scalable and is based on an array of interconnected, programmable, 32-bit RISC processors derived from the Sun SPARC architecture. It plans to develop a range of devices using the architecture, the main focus being on high definition encoding, transcoding and decoding and targeted at mobile phones.
"This multi-processor array approach with its user-configurable application software library is very different from the approach taken by other solution providers who use combination of FPGAs, general purpose processors, DSPs and hardware accelerators," says Ian Walsh, CEO of MnD.
Walsh adds the architecture allows a range of devices to be statically developed or dynamically configured for different price and performance points, all running the same software, giving significant economies of scale and reducing the cost, risk and time for system developers.
The architecture has been proven in FPGA implementations and Walsh says some customers are already shipping full custom chips based on the underlying technology into cost sensitive and competitive markets.
Unlike traditional approaches where the required processing power is achieved by having a single processor working flat out, the company says with Silver Screen, the array of processor cores running at lower processing speeds that aggregate together to deliver the required processing.
The cores in the array are very small and consume very little power, which even when all added together, provides a solution that is smaller, cheaper and less power hungry than a single high performance core solution with accelerators. Power consumption can be further reduced by switching off cores when not required.
The company has also developed a methodology for adding application specific instructions to the processor and programmable coprocessors in hardware to further accelerate math intensive algorithms.
For HD video encoding, decoding and transcoding, a single multiprocessor chip can be implemented on a 65-nm process, in conjunction with fully tested software libraries.
The architecture will scale to handle encoding of multiple channels of video up to resolutions of 1080p at 50 frame/s, as well as transcoding. The company says real time encoder manufacturers could use the device to replace the many expensive FPGA and DSPs that are currently used to implement the compression algorithms.
One or more of the chips can be interconnected and cost effectively scale for more complex higher performance multichannel and professional broadcasting applications.
The Silver Screen chip will also include an industry standard processor core for OEM use with an API to the HD codec array, as well as DDR interface for memory and an HDMI for displays.