SAN FRANCISCO Cadence Design Systems Inc. Monday (Sept. 18) announced the availability of an intellectual property (IP) portfolio intended to enable engineers to optimize Double Data Rate 2 (DDR2) interfaces on printed circuit (pc) boards and expedite the design process.
According to Cadence (San Jose, Calif.), the Allegro DDR2 design-in IP portfolio. features a methodology for designing system-level DDR2 memory interfaces, input-output models, pc board constraints and reference design material from memory and FPGA suppliers.
The initial offering includes a memory board reference design featuring Altera Corp.'s Stratix II FPGAs and DDR2 SDRAM megacore function memory controller, as well as Micron Technology Inc.'s DDR2 SDRAM DIMM, Cadence said.
IP from additional controller and memory suppliers will be added to the portfolio to create an environment in which systems designers can perform what-if analysis with multiple IC suppliers, Cadence said.
The design-in IP from Micron contains IO, package, and DIMM board models for their popular DDR2 devices, according to Cadence. Micron has also correlated the IBIS models with transistor-level models, Cadence said, in an effort to build the confidence of users of the design-in IP portfolio that DDR2 simulations with Allegro PCB SI are accurate and dependable.
The Cadence DDR2 design-in IP portfolio is available for download from the company's Web site, Cadence said.