Altera Corporation and Northwest Logic have announced the immediate availability of a hardware-proven, 667-Mbps DDR2 SDRAM interface for Altera's high-density Stratix II and Stratix II GX FPGAs. This interface combines Altera's auto-calibration DDR2 PHY and Northwest Logic's full-featured DDR2 SDRAM Controller Core to significantly simplify DDR2 SDRAM interface design while maximizing memory throughput.
Altera's DDR2 PHY has been optimized to provide robust performance over process, voltage and temperature variations. It is supported by a complete set of technical documentation, software and tools, intellectual property (IP) cores, demonstration boards, characterization reports and simulation models, all designed to help designers successfully interface Altera FPGAs to DDR2 SDRAM. Customers can contact their sales representative or visit www.altera.com/memory for more information.
Northwest Logic's DDR2 SDRAM Controller Core is part of a family of high-performance, easy-to-use memory controller cores which provide support for double data rate 2 (DDR2), DDR, mobile DDR, single data rate (SDR), mobile SDR SDRAM, and reduced latency DRAM II (RLDRAM II) memories. The DDR2 SDRAM Controller Core provides high bus efficiency using request reordering, bank management and look-ahead processing. Northwest Logic also provides Error Correction Code (ECC), Read-Modify-Write and Multi-Port Front-End add-on modules to further simplify user designs. The core supports the highest memory clock rates, requires a minimal gate count and comes with complete documentation and a verification suite. For more information contact Northwest Logic. Customers can download Northwest Logic's DDR2 SDRAM Controller Core from Altera's IP MegaStore website at www.altera.com/memorycontrollers.
To learn more about Altera's Stratix II FPGAs, visit www.altera.com/stratix2. To learn more about Altera's Stratix II GX FPGAs, visit www.altera.com/stratix2gx. To learn more about Northwest Logic's memory controller cores, visit www.nwlogic.com.