LONDON ARC International plc is developing a scalable multiprocessor architecture aimed at high-definition streaming media and graphics applications called VRaptor. The company's chief scientist Nigel Topham is due to present the architecture to the Fall Processor Forum on Tuesday (Oct. 10).
The architecture is expected to give rise to a number of licensable implementations provided with canned routines for MPEG4 and H.264 applications, set to be released in 2007. In addition ARC will provide architectural licenses and tools to allow customers to design their own multiprocessor architectures and map media processing software to the resulting processor arrays.
VRaptor offers a number of refinements over ARC's current offering for media applications, which is known as ARC Video. VRaptor is based on ARC 750D CPUs. ARC has extended the 128-bit SIMD array that was present in the ARC Video so that it is software programmable and becomes a media processor, off-loading work from the ARC 750D. In addition, the architecture allows clusters of ARC750s together media processors to be arranged flexibly to perform graphics and streaming media loops.
Legacy “fixed architectures” aren’t well suited to meet the requirements of complex, yet power sensitive, media-oriented processing tasks. A generic 32-bit RISC processor could require as much as 18-GHz for standard definition (SD) H.264 encode or 5-GHz for MPEG-4 encode, ARC said. ARC’s VRaptor Media Architecture will require only 200 MHz for SD H.264 encoding, while retaining all of the benefits of a programmable solution.
The VRaptor architecture with its parallelization is expected to scale from simple MP3 decode to complex HD H.264. At the same time developers should be able to keep clock frequencies down at a few 100-MHz or even reduce clock frequency if the processing load is spread across more processors, according to Peter Hutton, senior vice president of engineering at ARC (Elstree, England).
VRaptor supports multiple applications with media extensions, multiple vectorized 128-bit SIMD processors, high performance streaming I/O, and domain-specific accelerators. The various blocks can be joined together as appropriate by 32-bit wide point-to-point active communications channels architecture.