San Jose, Calif. CEVA, Inc.'s newest DSP core called the CEVA-X1641 is fully compliant with the company's CEVA-X Instruction Set Architecture (ISA) and the first Quad-MAC DSP core in the scalable CEVA-X family.
The core has been designed specifically to run highly computational intensive tasks that require substantial data throughput and high memory bandwidth. It is also fully synthesizable with enhanced memory architecture. This provides customers with the flexibility to configure the optimal memory size and structure for their specific application such as WiMAX, WiBro, 3G Long Term Evolution (LTE), or advanced multimedia standards, including the evolving H.264 compression standard and VC1 main profile. In defining the CEVA-X1641, CEVA worked closely with a lead customer that chose to utilize the CEVA-X-1641 for its WiMAX product line.
Like other CEVA-X ISA compliant cores, CEVA's latest DSP core is a combined VLIW/SIMD architecture, with additional features and enhancements required to handle the high-performance and data-throughput requirements of 4G technologies and multimedia applications. Highly computational intensive technologies such as WiMAX are calling for the use of 4 MAC units, coupled with a 128bit data memory bandwidth, to handle the extremely high data rates capable of reaching 100Mbps.
Furthermore, CEVA-X1641 incorporates specialized video instructions and mechanisms to accelerate multimedia processing in applications like mobile TV and video conferencing, while reducing frequency and power consumption to extend the battery life of these fully featured mobile multimedia devices.
"The CEVA-X1641 DSP core is in line with our strategy to offer platforms that will support the growing need for performance and power-efficient DSPs for emerging wireless and multimedia standards," said Gideon Wertheizer, CEO of CEVA, Inc. "Our new, high-performance and fully synthesizable CEVA-X1641 DSP core will enable customers to expedite their time-to-market and reduce development costs by using the same platform across multiple, differentiated products."
The CEVA-X1641 is upward compatible with CEVA-X1620 and CEVA-X1622 DSP cores, enabling licensees of the CEVA-X1641 to leverage the broad range of software and components already available for the CEVA-X architecture. In addition, the CEVA-X1641 architecture is implemented in a small size, only 5 percent larger than its Dual- MAC predecessor, the CEVA-X1620.
In addition to four MAC units operating in parallel, the new core offers twenty-four 40-bit accumulators, 128-bit data bandwidth, 8/16/32/40bit data operands and operations, and 16/32bit instructions. The VLIW architecture allows a high level of concurrent instructions processing thus providing extended parallelism, as well as low power consumption. SIMD architecture allows single instructions to operate on multiple data elements that result in code size reduction and increased performance. Low power consumption is achieved in the CEVA-X1641 by its efficient instructions and dedicated mechanisms such as dynamic and selective unit shutdowns and clock gating.
For details of the chip, see block diagram below:
See related image
The CEVA-X1641 provides a high-performance, low-power platform allowing its licensees to develop multi-mode products (e.g., 2G/3G/4G processors) and to reuse the same platform for next-generation standards such as 802.16e, WiBro, Flash-OFDM, UMTS and TD-SCDMA.
The CEVA-X1641, together with a complete software development tool chain, is available for immediate licensing. The licensing cost was not released.
CEVA,Inc. (408) 514-2976