Portland, Ore. -- Two companies are developing rival automotive machine vision solutions using inexpensive digital cameras. But while International Electronics & Engineering S.A. (IEE) has crafted a sensing system based on a combination of 2-D and 3-D cameras, Mobileye Inc. has opted to use a normal 2-D camera.
A charge-coupled device chip from IEE (Luxembourg) uses an infrared beam to calculate distance. Its dynamic occupant-sensing system will control the passive restraint systems by detecting and classifying the occupant's size and position. Because the 3-D camera system is located in the central overhead console, it can monitor both front seats. In the event of deployment, the dynamic out-of-position sensing system mitigates the air bag's strength and accelerates its firing time.
IEE's chip, the Dynadis, detects the optical time of flight for a modulated light intensity from near-infrared light-emitting diodes. The reflection of the modulated light is measured on a pixel-by-pixel basis on the company's CMOS CCD image chip.
Meanwhile, a CMOS hardware accelerator chip from Mo- bileye Inc. (Southfield, Mich.) employs sophisticated software that analyzes perspective to calculate distance but uses a normal 2-D camera feed to do so. "I find [that] fascinating," said David Alexander, senior analyst at ABI Research (Oyster Bay, N.Y.).
Instead of selling a camera, Mobileye sells a custom ASIC that performs the distance calculations using any off-the-shelf video camera. Called EyeQ, Mobileye's system-on-chip uses the camera to perform real-time visual recognition and scene interpretation.
EyeQ is fabricated using a standard CMOS 180-nanometer process, operates at 120 MHz and supports two simultaneous 12-bit 640 x 480 color-image-resolution video streams.
Mobileye's ASIC uses parallel visual-processing units that rival a Pentium IV running at 4 GHz, according to the company. The ASIC houses two 32-bit ARM 946E CPUs, plus four vector-based vision-computing engines and multichannel direct memory access (DMA). For ultrahigh performance, chips can be arranged in up to a 4 x 4 matrix, with high-speed, 64-bit DMA to a shared 288-kbyte on-chip SRAM.