Sarance Technologies, a leading networking IP vendor, today announced the immediate availability of an Interlaken intellectual property (IP) core for Xilinx Virtex-5 FPGAs. Interlaken is the next generation high-speed serial chip-to-chip protocol for transferring packets in networking systems. The availability of the IP core provides networking system manufacturers a low risk path for developing their next generation equipment.
"We have implemented a very efficient and flexible Interlaken IP core targeted for the high performance Xilinx 65nm Virtex-5 Platform," said Farhad Shafai, Vice President, R&D at Sarance Technologies. "Our standard offering goes up to 40Gbps of payload bandwidth today, but the IP's architecture is scalable, much like Interlaken, and allows us to build higher bandwidth cores as system performance increases."
"Interlaken is steadily gaining traction within our Tier One customer base, demonstrating its potential to become the de-facto packet-based interface," said Amit Dhir, director of Infrastructure Vertical Markets at Xilinx. "By leveraging our 65nm Virtex-5 FPGA high- performance architecture and low power SERDES, customers have a highly-scalable solution, enabling optimized connectivity in a wide range of Internet Protocol-based Infrastructure Equipment designs."
Price and availability
Interlaken cores for the Xilinx Virtex 5 FPGAs are available from Sarance Technologies now for 12.5-Gbps, 25-Gbps and 40-Gbps data rates. For information on other configurations and pricing, please contact Sarance Technologies at firstname.lastname@example.org.
About Sarance Technologies
Sarance Technologies is an intellectual property development firm based in Ottawa, Ontario, Canada. Sarance offers a portfolio of ASIC and FPGA silicon IP cores targeted at vendors developing data communication solutions. Sarance specializes in developing classification engines, high speed interconnect, and other building blocks used in typical networking line cards. Sarance also offers consulting services for integrating its IP into FPGA or ASIC designs.