San Francisco -- With the stated goal of enabling product development teams to more effectively define, measure and achieve goals when using the SystemVerilog unified hardware description and verification language, Synopsys Inc. this week will introduce three components designed to enhance a methodology for SystemVerilog verification created by Synopsys and ARM Ltd.
Since its publication in September 2005, the Verification Methodology Manual for SystemVerilog, or VMM, has become the de facto standard methodology for system-on-chip verification and has been used by hundreds of design teams globally, Synopsys said. Its authors are Janick Bergeron and Eduard Cerny of Synopsys (Mountain View, Calif.) and Alan Hunter and Andrew Nightingale of ARM. VMM is also endorsed by Starc, the Japanese semiconductor R&D consortium.
But while the VMM methodology provides a foundation for verification and a guide for writing testbenches, it doesn't necessarily shoulder the verification workload, said Swami Venkat, director of product marketing for RTL verification at Synopsys. "What VMM does is provide a blueprint for creating the verification architecture," Venkat said. "The engineer still has a lot of work to do in terms of creating the testbenches and managing the verification process."
Enter the three enhancements: VMM Planner, VMM Applications and VMM Automation address verification predictability, development productivity and execution/analysis productivity, respectively.
According to Synopsys, VMM Planner enables managers to systematically plan and track verification progress to increase the predictability of the process. It helps design teams track the status of projects by systematically capturing a feature hierarchy of the design to be verified.
VMM Applications reduces testbench creation time by allowing architects to quickly construct more effective verification environments, Synopsys said. It provides a collection of high-level functions to reduce testbench creation for commonly used design elements.
VMM Automation improves the productivity of engineers developing and using advanced testbenches. It provides tools and features to improve the productivity of verification, Synopsys said.
According to a testimonial provided by Synopsys, Tim Houlihan, verification manager at Cypress Semiconductor Corp., said that using VMM Applications saved the company two months of work.
Venkat said the three enhancements will be part of the company's VCS functional verification solution and Pioneer-NTB testbench automation tool at no additional cost to customers. VMM Planner and VMM Applications are available now in beta form, he said, while VMM Automation tools will be become available during the next two years.