MONTEREY, Calif. EDA vendors Synplicity, Novas Software and Cypress Semiconductor have introduced software tools aimed at streamlining the system-on-chip (SoC) design cycle and semiconductor verification process. The companies announced their products at the Globalpress Electronics Summit here Tuesday (Feb. 27).
Synplicity Inc. (Sunnyvale, Calif.) said its TotalRecall technology offers the debug visibility of a hardware emulator, but at speeds ranging from 10 to 100 times faster. Novas Software Inc. (San Jose, Calif.) introduced Replay, a visibility enhancement to its Siloti software suite, which the company claims adds timing-accurate simulation replay capabilities. And Cypress Semiconductor Corp. (San Jose) unveiled its CapSense software, which adds capacitive-sensing replacements to mechanical buttons for users of its Programmable System-on-Chip (PSoC) software tool.
Synplicity's TotalRecall allows design engineers to capture all of the signals in an ASIC during the design process. This includes memory contents, and it can be done at any user-specified number of clock cycles before an error is detected, like a hardware emulator. Unlike a hardware emulator, however, TotalRecall lets users export the complete design state, along with the automatically generated testbench, to an HDL simulator. There the sequence can be replayed.
Total Recall, the company claims, lets designers repair problems within the simulation environment using the same signal values that led to the error in the first place. For example, Total Recall can simulate errors in a bootup on a cell phone FPGA prototype running at 20 MHz in three seconds, compared with 30 days for a software simulator alone, said the company.
Replay, an add-on module to Novas Software's Siloti Visibility Enhancement software suite, enables the detection, isolation and repair of timing problems using gate-level simulations. The company claimed Replay enables a 10-fold smaller file dump size while providing faster and more accurate results during the debugging of timing problems. Replay reduces signal data-recording requirements by limiting the initial data dump to signals relevant to the timing problem being debugged.
Instead of simulating all signals simultaneously, Replay enables short, targeted simulations that capture timing-accurate signal data. But the data does not have to run through all the previous states to begin at a user-defined point. Simulation can be rerun any number of times, using different timing windows but drawing from the same baseline signal dump.
Cypress' CapSense is an add-on to its PSoC development suite for mixed-signal arrays. It enables touch-sensitive buttons, sliders and similar control surfaces to be added to designs at a high level, and it does not require assembly or C programming.
PSoC already had an array of input/output devices in its catalog that let designers link them together to define system behavior. Previously defined I/O devices included temperature sensors, voltage inputs, fans and LEDs. Now designers can also add capacitive buttons and sliders to the list.
Capacitive sensors decrease the bill of materials, since there is no mechanical switching involved. All that is needed to define a capacitive sensor is a copper pad on the printed-circuit board, which is then covered by the device's existing front plate.
CapSense is free and can be downloaded from Cypress' Web site.