NETANYA, Israel Startup Mplicity Ltd. (Tel Aviv, Israel) has developed a technology that it claims can, working from an original netlist, turn a single-threaded system, be it a processor or any other combinatorial logic, into a multithreaded system, with a performance improvement of up to a factor of four.
Mplicity's software is called CoreUpGrade and is independent of processor architecture, the company said. "The CoreUpGrade seamlessly transforms a given single-processor core into an enriched multi-core with a significantly reduced cost to performance ratio; it is also designed to compress large blocks of any repetitive logic," the company claimed at its website.
CoreUpGrade can provide support engineers who want to perform an engineering trade-off between die area and clock frequency which equates to a business trade-off between cost and power consumption.
Providing an example CoreUpgrade's capability Mplicity has taken a single-core ARC625D from ARC International plc (Elstree, England) capable of performing at a 270-MHz clock frequency and transformed it into a dual-core processor capable of performing at 237-MHz clock frequency across the two cores. The result is an silicon die area of 0.484 square millimeters, instead of 0.354 square millimeters but with 27.5 percent improvement in MIPS/area ratio, Mplicity said.
The "dualized" ARC625D is a cycle-by-cycle compatible component which can be integrated with standard EDA tools and fab processes.
CoreUpGrage is applicable for any repetitive logic and can be used to optimize a variety of existing RISC, CISC and DSP processor netlists, by enhancing processor performance, while reducing silicon footprint and power consumption.