Hillsboro, Ore. Lattice Semiconductor Corporation has released its PURESPEED I/O burst mode receiver (BMR) FPGA reference design for Gigabit Passive Optical Networks (GPONs). This reference design uses Lattice's unique Adaptive Input Logic (AIL) block found on its LatticeSC and LatticeSCM FPGAs to rapidly establish stable clock to data timing relationships within the fast lock times specified in the GPON ITU-T G.984.1 specification, which requires the Optical Line Termination (OLT) to lock to incoming data within 50 bit times.
The Lattice BMR solution leverages the fast locking, low latency AIL circuitry in the PURESPEED I/O to perform the data recovery, making it the smallest footprint (256 BGA package) and lowest power (150 mW) FPGA-based BMR solution available, according to Lattice. AIL is one of the key building blocks within the PURESPEED I/O architecture featured on the LatticeSC/M family of FPGAs. Other key components of the PURESPEED I/O include high-performance I/O buffers with dedicated logic, built-in shift register and DDR/SDR Mux/Demux logic, and dedicated clock divider circuitry for by-2 and by-4 clock division.
Integrated into the LatticeSC devices are high-channel count SERDES blocks supporting 3.8 Gbits/s data rates, PURESPEED parallel I/O providing 2 Gbits/s speed, innovative clock management structures, FPGA logic operating at 500 MHz and massive amounts of block RAM, said Lattice.
Product information: reference design and user's guide, GPON application note, and GPON presentation
Lattice Semiconductor, 1-503-268-8000, www.latticesemi.com