LONDON The prototype of a novel polymorphous general purpose microprocessor architecture being developed and built in the Department of Computer Sciences at The University of Texas at Austin, is due to be unveiled on Monday (April 30) at a public presentation on the university campus.
The TRIPS (The Tera-op, Reliable, Intelligently adaptive Processing System) processor has been in development for more than seven years and is being billed as an architecture that will be able to scale until the end of the silicon era. Sponsors of the technology include IBM, Intel and Sun Microsystems Inc.
The research team, led by Professors Doug Burger, Stephen Keckler and Kathryn McKinley, has been working on the design of the processor, a cross-platform compiler and an instruction set architecture. The goal has been to produce a scalable architecture that can accelerate industrial, consumer, embedded and scientific workloads, reaching trillions of calculations per second on a single chip.
While the development of the TRIPS processor has largely been an academic exercise over the last several years in the theory of parallel and multiprocessing, the fact that commercial processors have recently gone "multicore" is giving TRIPS added resonance and traction right now.
The TRIPS architecture, based on Explicit Data Graph Execution (EDGE), can produce improved single-thread performance at better power efficiencies than conventional designs, the development team claims. The goal is to accelerate industrial, consumer, embedded, and scientific workloads, reaching trillions of calculations per second on a single chip.
Most current processors were originally designed as uniprocessors. Performance can be improved by adding more processors, but this often puts a burden of parallelization on software writers a burden they are frequently not prepared to shoulder. It is also hard to overcome inefficiencies of intra-processor communications as the number of processors is increased. The most successful examples of multiprocessor designs have been where the processor is application specific and a uniprocessor programming model can be presented to software writers through the use of in intermediate hardware abstraction layer.