San Jose, Calif.Optmized for the mobile handset market, Inapac Technology Inc. is sampling a 16-Mbit SDRAM design based on its high-volume SiPFLOW platform that incorporates a design-for-test (DFT) architecture and production methodology.
For more on the SiPFLOW platform, click here.
According to Inapac, the SiPFLOW platform enables SiP and MCP producers to minimize cost of ownership while achieving production quality and reliability. The total cost of incorporating the 16-Mbit memory die would be less than 50-cents per SiP/MCP in volume production, further extends their reach in high-volume consumer markets where their average selling price is $5 or less, the company said.
Inapac's SiPFLOW platform is licensed to SiP and MCP suppliers addressing such applications as feature-rich cellular handsets, personal media players and LCD-based displays.
"The new design enables smaller packages, lower power and lower-cost implementations," said Naresh Baliga, vice president of marketing for Inapac, in a statement. "The new design offers a bond-pad-compatible transition from the existing design, and is manufactured on the proven, high-volume 0.12-micron DRAM wafer foundry from ProMOS Technology."
Availability: Sampling in second quarter of 2007; volume production planned for the first quarter of 2008.
Datasheets: click here.
Inapac Technology Inc.,1-408-434-6530, www.inapac.com