Certess Inc. today (May 7) launched Certitude, a functional qualification software product for companies developing systems on a chip (SoCs) or integrating intellectual property (IP) blocks. It addresses one of the larger problems in functional verification the absence of objective quality assurance in SoCs and IP blocks.
Certess announced itself in March as a venture-funded startup launched to develop "functional qualification" technology, described as a way of verifying the IC verification process itself. It promises to go far beyond today's code- and functional-coverage metrics, and tell verification engineers whether or not bugs in the design may be undetected.
Verification people have tried to use some types of coverage metrics to gauge completeness. Unfortunately, coverage doesn't equate to completeness. Existing coverage tools, however, only measure the activation portion of the flow; they tell you if a line of code was accessed. They cannot measure propagation or detect any errors on the outputs, Certess claims.
There are three aspects to verifying any design structure. Activation is the ability to get a vector to the design under investigation. Propagation is the ability of those data to get through the design. And detection is the ability to see results of that data propagation. A verification run is considered complete only if all three elements are available. If the data output doesn't match the expected output, there is some type of error in the circuit.
According to Mark Hampton, CTO of Certess, "the technology for this tool is based on research in the software domain and has been under investigation in academia since 1978. The technology, mutation-based analysis, inserts small changes in the code and tests to see if the mutation propagates through to some output. If the effects of the mutation are not detected at the output, then a bug could exist in that section of code and that bug would not be detectable."
Their implementation applies new algorithms to create an automated, scalable environment. The tool uses an automated static process to analyze the design and determine where to insert faults. The tool requires a number of inputs the design files in Verilog or VHDL, and a list of test case files to identify the tests.
The user needs to generate two additional files. One is a compile script that lists the names of the instrumented design files, and the other is an execute script, a batch file that indicates which and in what order to execute the test files. The output of the tool is an HTML report and cross-linked code window.
Current tool implementation is for RTL verification. All interfaces to the HDL simulators are through APIs. Therefore, Certitude is isolated from the verification environment and is able to operate in any simulation environment including SystemC, SystemVerilog, Verilog, VHDL or even mixed language simulations.
Future plans include SystemVerilog in the later part of this year, and SystemC further down the road. There is no direct interface to formal tools, so the current tool requires a lot of data manipulation to transfer information from a formal tool to the Certitude tool.
In a recent verification survey conducted by E-mail Synopsys Users Group (ESNUG) moderator John Cooley, several engineers offered their impressions of Certitude.
Xavier Jacquart of STMicroelectronics offered praise. "Since last year, I use another tool called Certitude from Certess," he said. "This tool is now mandatory in our verification flow. It allows us to get metrics and answer the question: how confident could we be in our verification to release the chip and tape out? We can identify exactly the risk we take releasing the chip with the verification level we have achieved."
Certitude is available now starting at $100,000 per year for a time-based license.