Hoping to make low-power IC design techniques more accessible, Cadence Design Systems this week is announcing its Low-Power Methodology Kit. It complements existing Cadence design and verification tools with a "representative" design, example intellectual property (IP), and scripts and libraries.
The kit adds to the Low Power Solution that Cadence rolled out in January. That solution promises a complete design and verification flow for low-power ICs, based on the Common Power Format (CPF) that was developed by Cadence and is now managed by the Silicon Integration Initiative (Si2).
Many IC designers, however, are struggling with low-power design techniques like multiple supply voltages and power shutoff. As a result, tools alone aren't enough, Cadence representatives say.
"More people need to deal with low power, and fewer people have the necessary knowledge to go off and do it," said Neil Hand, director of Cadence's verification solutions group. "We need to make low power implementation available to a wider audience."
To that end, the Low-Power Methodology Kit includes a wireless "representative design" implemented using multi-supply voltage and power shutoff methods. It comes with all the necessary command scripts and technology files to complete the design. The design also comes with sample IP including a processor and bus fabric from ARM, WiFi from Wipro, USB 2.0 from ChipIdea, 65 nm low-power memories from Virage Logic, and 65 nm technology libraries from TSMC.
It's not quite the same thing as a reference design, Hand said. "For many people, a reference design means this is the way you should do your design," he said. "A representative design is intended to capture the kinds of challenges people face, and to show how we solved them. It's a subtle difference but an important one."
The sample IP is for use in the representative design only. If customers want to use the IP in a production design, they'll need to license it from the third party provider.
The Cadence kit also includes scripts, methodology documents, and flow checklists. "We've tried to capture knowledge that makes it easily distributed to people of all skill levels," Hand said.
The Low-Power Methodology Kit is modular and includes six flows: low-power functional simulation, logic synthesis, design for test, physical design, formal implementation, verification, and power grid signoff. Users can implement the entire kit or select modules individually. The kit will be available in late June.