San Jose – Fabless silicon IP vendor CEVA Inc. has introduced the CEVA-TeakLite-III family of DSP cores and the first three family members, the TL3210, TL3211, and TL3214. The new cores target 2.5G and 3G cellular baseband, high definition audio, VoIP, and portable audio players. The TeakLite-III cores are assembly code compatible with previous generation TeakLite cores, but the new cores incorporate many significant enhancements.
Of particular interest to DSP developers is the addition of 32-bit and dual 16x16-bit multipliers. (The TeakLite I and II have only a single 16-bit multiplier.) The 32-bit multipliers offer the increased precision needed for high-fidelity audio applications, while the dual 16x16-bit multipliers boost performance for a wide range of DSP applications. The TeakLite-III also gets a speed boost from new audio-oriented instructions and instructions for accelerating FFT, Viterbi, and Huffman algorithms. Initial performance estimates by CEVA show TeakLite-III cores to be 4x faster than previous TeakLite cores on basic operations and 2x faster on most popular audio codecs.
The new cores will run at 350 MHz in a 90nm G process and up to 425 MHz in a 65nm G process, under worst case conditions. The increase in clock speed is largely enabled by deepening the pipeline to 10 stages, up from 4 stages in previous TeakLite cores. CEVA has also introduced pipelined memory accesses to allow memory to keep pace with the higher clock rates.
Other changes include migration to a 32-bit architecture (TeakLite I and II were 16-bit architectures) and new RISC features. The new RISC features include
- A 32-bit general purpose register bank
- A 32-bit linear address space that extends the addressable memory to 4 Gb
- A cached memory subsystem that frees the developer from managing memory
- Branch prediction and conditional instructions, both of which improve the performance of decision-making code
The TeakLite-III nominally uses 32-bit instructions, but it also supports a comprehensive 16-bit instruction set dubbed CEVA-Quark. An entire application can be written using only the 16-bit Quark instructions, or programmers can mix 16- and 32-bit instructions. This allows developers to make trade-offs between code size and performance. (Other instructions sets, such as the ARM Thumb2 instruction set, offer similar capabilities.)
TeakLite III continues the trend in DSP cores of incorporating more control functionality. It will likely compete against other dual-MAC DSPs such as the C55x+, which runs at 400-500 MHz under worst case conditions. It will also compete with 32-bit RISC processors which incorporate DSP functionality, such as the ARM11 and MIPS24KEc cores.
CEVA reports that two top tier Semiconductor vendors have licensed TeakLite III cores; a US-based vendor developing a multi-mode baseband chip, and an Asian vendor developing chips for high definition audio applications.
The CEVA-TL3210 and TL3214 are available for license today. The TL3211 is slated for licensing in early 2008.