SAN JOSE, Calif. Bringing a number of high-end computing technologies to the embedded world, MIPS Technologies Inc. Tuesday (May 22) unveiled its new RISC-based, 32-bit processor architecture. The IP core includes a superscalar, out-of-order technology for use in a range of high-performance applications.
The MIPS32 74K line from the company consists of two synthesizable, 1.04-GHz cores, dubbed the 74Kc and 74Kf. The 74Kc is a base integer core, while the 74Kf combines the integer core and a high-performance floating-point unit.
Based on a 65-nm process technology from silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), the 74K is built around a superscalar, 17-stage pipeline architecture with enhanced digital signal processor (DSP) instructions.
Unlike its previous 32-bit, RISC-based embedded cores, MIPS' 74K product makes use of a number of technologies normally found in high-end computing: out-of-order dispatch, asymmetric dual-issue, branch prediction and a 128-bit L1 cache interface. The 74K is a single-threaded core, but future product may include a multi-threaded technology
Despite the use of such technologies, the 74K is by no means considered overkill for new and future embedded applications, said Pete Del Vecchio, product marketing manager for MIPS Technologies (Mountain View, Calif.). ''For low-end processing, it is really not appropriate,'' Del Vecchio said. ''But for certain applications, you need this level of performance.''
The 74K is designed for high-volume applications, such as DTV, set-top boxes, DVD players/recorders, broadband access systems, residential gateways and other systems, he said.
The new product expands MIPS' efforts in the 32-bit embedded processor space, where it competes against ARC, ARM, among others. Previously, MIPS' high-end embedded processor core was the 24K, an 8-stage, single-issue architecture based on 90-nm technology.
The 24K is not based on an out-of-order architecture. But the out-of-order instruction dispatch technology within the 74K enables the new core to execute multiple instructions, enabling improved processor performance, according to MIPS. In total, the 74k has an overall performance of 1.8-DMIPS/MHz, according to the company.
The 74K also supports advanced branch prediction, thanks to three 256-entry branch history tables and an 8-entry return prediction stack. It also features enhanced DSP instructions, which are 60 percent faster than the 24KE cores from MIPS. It also supports L2 cache and extensive clock gating for low-power applications.
The high-end, 74Kf supports a high-performance floating point unit, which consists of two pipelines based on an asymmetric dual-issue architecture.
The 74Kc has a core area of 1.7-mm2 and a total area of 2.5-mm2. It supports 32-K of data cache and 32-K of instruction cache. It consumes 34 mW of power. The 74K family is now available.