Lattice Semiconductorhas announced the immediate availability of 45 ispLeverCORE Intellectual Property (IP) and third-party vendor IP cores for its new 90 nanometer embedded FLASH LatticeXP2 FPGA family. Lattice and its ispLeverCORE Connection partners – CAST, ANAGRAM Technologies, DCD, Eureka Technology, and WDC – have already ported a wide range of cores addressing automotive, communications, consumer, embedded, instrumentation, video and wireless applications to the LatticeXP2 architecture.
"Our goal is to provide 'More of the Best' IP solutions for every device family at product introduction. Our new 90nm LatticeXP2 family provides a third generation non-volatile FPGA platform for Lattice and its IP partners so we can deliver even more value-added solutions to our mutual customers," said Stan Kopec, corporate vice president of marketing. "The wide range of third-party cores available builds on the unique value of the LatticeXP2 devices and creates tremendous mutual opportunities for Lattice and our partners."
IP partners praise the LatticeXP2 FPGA family
"The exciting new LatticeXP2 devices are like our cores – lean and efficient, yet packed with functionality and ready to work right away," said Hal Barbour, president of CAST. "We're pleased to offer the first configurable 8051 core for the LatticeXP2 family, and are rapidly porting many of our 100+ cores to the new technology."
"Once again Lattice is at the leading edge of the on-going trend toward reconfigurable, fully integrated architectures that offer attractive benefits in terms of power consumption, cost, and time-to-market," said Tim Llewellyn, vice president of sales and marketing for ANAGRAM Technologies. "By adding DSP capabilities to the LatticeXP2 devices, customers can now benefit from our SoftAMP Class D PWM Amplifier and SoftDAC 24bit Audio DAC IP running on the industry's most integrated reprogrammable devices."
"We have developed hundreds of IP cores across different platforms. Migrating our IP to the LatticeXP2 devices was one of the easiest transitions we have experienced," said Simon Lau, president of Eureka Technology Inc. "We were able to achieve maximum performance with minimal effort. All of Eureka's IP cores support the LatticeXP2 FPGA family."
"We are very excited to have an opportunity to work with the new LatticeXP2 technology and have already been working with customers using DCD's IP cores inside these chips," said Tomek Krzyzak, vice president of IP development at DCD. "The most popular of DCD's products in Lattice's ispLeverCORE Connection program have already been ported to the LatticeXP2 devices with great success."
"Our LatticeXP2 implementation of the 65xxx microprocessor IP provides a flexible, instant-on emulation of our ASIC hard cores. Users can use this for prototyping, or stay with the low-cost LatticeXP2 devices into production," said David Gray of Western Design Center. "The legendary flexibility of the 65xxx secures a wide breadth of applications not available with other 8-bit cost effective processor families. The LatticeXP2 devices showcase this."
Software design support
Lattice-developed ispLeverCORE IP cores for the LatticeXP2 family are supported by the recently released version 7.0 of the ispLEVER design tool suite via Lattice's IPexpress flow, included as a standard feature in the ispLEVER software. The cores include:
- Block Convolutional Encoder
- Block Viterbi Decoder
- Cascaded Integrator-Comb (CIC) Filter
- Color Space Converter
- Dynamic Block Reed-Solomon Decoder
- Dynamic Block Reed-Solomon Encoder
- DDR Memory Controller
- DDR2 Memory Controller
- FFT Generator
- Numerically Controlled Oscillator (NCO)
- PCI Master/Target 32-bit, PCI Master/Target 64-bit, PCI Target 32-bit, PCI Target 64-bit
- Tri-Speed Ethernet MAC
- Turbo Encoder
IP cores from Lattice's ispLeverCORE Connection partners are also supported by version 7.0 of the ispLEVER design tool suite. The following cores are available (listed by vendor):
- ANAGRAM Technologies – SoftAMP Digital Class-D Controller, SoftDAC 24-bit Audio DAC.
- CAST – CAN Bus Controller, H16550S Synchronous UART with optional FIFO, R8051XC Configurable 8-bit Microcontroller, SDLC Controller, Baseline JPEG Codec, Baseline JPEG Decoder, Baseline JPEG Encoder.
- DCD – Serial Peripheral Interface-Master/Slave, Serial Peripheral Interface-Slave, Serial Peripheral Interface-Master/Slave with FIFO, D16450 Configurable UART, D16550 Configurable UART with FIFO, D16750 Configurable UART with FIFO, DI2CSB I2C Master, DI2CSB I2C Slave, DI2CSB I2C Slave Base Version, DP8051 8-bit Pipelined Microcontroller.
- Eureka Technology – CompactFlash/PCMCIA Host Adapter, NAND Flash Controller, PowerPC Bus Arbiter, PowerPC Bus Master, PowerPC Bus Slave, SD/SDIO Controller.
- WDC – W65C02SRTL 8-bit 65xx Microprocessor, W65C816SRTL 8/16-bit 65xx Microprocessor.
About Lattice ispLeverCORE IP modules
Lattice's ispLeverCORE modules are optimized for use with Lattice devices. The modules are large, modular design blocks, commonly known as intellectual property (IP) cores, which can be reused and easily placed within a programmable logic design. ispLeverCORE IP cores are configured for specific customer applications via the IPexpress module included within the ispLEVER tool. The IPexpress flow allows customers to parameterize IP on their desktop, incorporate the IP within their designs and evaluate the resulting design within their hardware before committing to purchase an IP license. The modules are designed using the highest coding standards and are extensively tested to meet the required functionality and performance. These cores are ready-to-use, well documented and supported by Lattice field and factory engineers.
About Lattice ispLeverCORE Connection partners
The ispLeverCORE Connection is a global organization of independent IP providers who have teamed with Lattice to bring its customers the highest quality, reusable IP cores optimized for Lattice's unique portfolio of FPGA devices. All Connection partners are selected for their industry leadership, high development standards and commitment to customer support. Lattice works closely with each Connection partner to ensure they have all the proper tools and training to maximize their cores' performance in Lattice's software and devices. Connection partners provide many widely used cores that are complementary to Lattice's own line of ispLeverCORE products. The ispLeverCORE Connection cores have been extensively tested and have a history of successful customer use.
About the LatticeXP2 family
The LatticeXP2 family combines a Look-up Table (LUT)-based FPGA fabric with FLASH non-volatile cells on a 90nm process technology, in an architecture called flexiFLASH. The flexiFLASH approach provides benefits such as instant-on operation, a small footprint, on-chip storage with FlashBAK embedded block memories, Serial TAG memory and the highest design security. LatticeXP2 devices also support live updates with Lattice's unique TransFR technology, 128-bit AES design encryption and dual-boot technologies. The family provides five devices ranging between 5K and 40K LUTs in a wide variety of packages.
Pricing and availability
All Lattice-developed ispLeverCORE IP modules are supported by the IPexpress design flow within ispLEVER version 7.0, available now. Click Here for User Guides for these IP modules. Lattice's comprehensive ispLEVER design software, providing support for all Lattice CPLDs and FPGAs, including IPexpress support, is priced at a low $695 for a complete Windows-based seat.
The ispLeverCORE Connection IP cores are available for purchase immediately from the respective ispLeverCORE Connection partners. Click Here for details of these cores.