In conjunction with the production release of the first devices in its acclaimed LatticeECP2M FPGA family, Lattice Semiconductor has announced dramatically lower price points for the industry's first low-cost FPGAs to offer high-speed embedded SERDES I/O. Production volume prices have been reduced to as low as $9.95 for the 20K Look-Up-Table (LUT) LatticeECP2M-20, substantially below those of competitive SERDES-capable FPGAs and cracking the $10.00 price barrier for the first time. When compared to Lattice's previously announced pricing, these prices represent a price reduction of >20% in less than one year.
Lattice Semiconductor has also announced that the LatticeECP2M family's performance has been boosted by up to 30% across a broad range of common logic macro-functions such as decoders, multiplexers, counters, and adders. These performance enhancements are supported by Lattice's new generation ispLEVER Version 7.0 FPGA design tool suite, and are the result of final device characterization along with optimized logic implementation by the design tools. In addition, Lattice is providing both standard and advanced evaluation boards, as well as an ever-expanding suite of 43 soft IP cores and reference designs developed by Lattice and its third-party IP partners, to complete and demonstrate a wide range of solutions for communications (e.g. CPRI), interface (e.g. PCI Express), Video Display, DSP, and other applications. Illustrating Lattice's commitment to deliver fully standard-compliant solutions, the LatticeECP2M PCI Express x4 solution was successfully tested against the PCI Express version 1.1 specifications at the recent February 2007 PCI-SIG compliance workshop.
"We chose the LatticeECP2M family for our latest Eclipse family of microwave radio links due to its ability to support the high performance SGMII Ethernet interface without the external devices I would have needed with other FPGA solutions," said Ruben Zarrabi, principal product development engineer for Harris Stratex Networks, Inc. "Also, my designs are memory intensive and the LatticeECP2M family provides 10 times more Block RAM than other low-cost FPGAs. In addition, the prices of the ECP2M devices are very attractive."
"We selected the Lattice ECP2M family because it provided us with the optimal mix of high-speed performance, logic density and distributed memory" said Lou Orsini, director of engineering at Spectracom, a leading developer of precision timing products. "Lattice has also provided us great support with design tools and IP that have allowed us to decrease our time to market."
High-volume, high-yield production drives cost reduction
Lattice is able to offer more aggressive prices and performance enhancements for the LatticeECP2M FPGAs as the first two family members (20K and 35K LUTs) are moved into production. The remaining three family members (50K, 70K and 100K LUTs) will be released to volume production over the next 60 days.
Lattice and its 90nm foundry partner, Fujitsu, have worked together to optimize product yields on the LatticeECP2M product family manufactured on Fujitsu's 300mm wafer fabrication line. Yield expectations for the initial devices have been surpassed at both wafer level testing and finished goods testing. These enhanced yields translate directly into lower product costs, which are helping to drive the price reductions being announced today.
"Lattice is changing the industry dynamic for low-cost FPGAs. Customers no longer have to choose between price and performance. With the LatticeECP2M family, they get both," said Steve Stark, Lattice's director of product marketing. "No other FPGA devices in the market can deliver a full, 4-channel PCI Express implementation in a space efficient 256 fpBGA package for under $10, but our LatticeECP2M-20 devices can."
Device characterization completion drives improved performance
The latest performance enhancements are the result of the completion of performance characterization of the first devices, as well as the more efficient logic map, place and route functions demonstrated by the ispLEVER design tools. These enhancements further improve the devices' best-in-class performance in the low-cost FPGA space. Many basic logic functions have now been demonstrated to perform at faster rates than originally specified. For example, 32-bit decoders are 30% faster, 64-bit adders are 22% faster and 16-bit counters are 7% faster. These faster timing specifications and algorithms are incorporated into ispLEVER Version 7.0.
Lattice's goal is to provide a full range of easy-to-use, tested and documented IP solutions for its FPGA products at the time of launch. Recent enhancements to the ispLEVER design tool set, such as its IPexpress IP management and configuration module, make configuring and evaluating Lattice IP solutions in both software and hardware quick and easy. Support to date for the LatticeECP2M family consists of cores developed by both Lattice and its IP partners DCD and ANAGRAM Technologies. (Click Here for a complete listing of all IP cores available to support the LatticeECP2M family.) Additional cores to be made available by Lattice as well as other members of its ispLeverCORE Connection program will be announced in the future.
About the LatticeECP2M FPGA family
The LatticeECP2M FPGA family has redefined the low-cost FPGA product category. Based on Lattice's second-generation, low-cost LatticeECP2 FPGA family, the LatticeECP2M family adds performance-enhancing features that are typically available only on competitive high-end FPGAs at a much higher price. The LatticeECP2M family supports logic densities from 20K LUTs up to 100K LUTs, has high performance DSP blocks, supports DDR2 memory interfaces at 533 Mbps and up to 840 Mbps generic LVDS performance. Some of the high-end features incorporated into the LatticeECP2M family include embedded SERDES I/O and the most on-chip memory in its class. The LatticeECP2M family supports up to 16 channels of embedded SERDES operating up to 3.125Gbps, supporting protocols such as PCI Express, Ethernet (1GbE and SGMII), CPRI and OBSAI. The LatticeECP2M Embedded Block RAM capacity ranges from 1.2 Mbit up to 5.3 Mbits, representing up to a 400% increase over competitive low-cost architectures.
Pricing and availability
Representative prices for production volumes (100K pieces or more) purchased directly from Lattice by its customers for delivery in 2008 start at $9.95 for the 20K LUT LatticeECP2M-20E-5FN256C in the 256 ball fine pitch Ball Grid Array (fpBGA) package and $46.95 for the 70K LUT LatticeECP2M-70E-5FN900C in the 900 fpBGA package.