Startup Tilera Corp. will disclose its Tile64, a massively parallel general-purpose embedded processor, at this week's Hot Chips conference. The chip promises to break ground in the effort to make CPUs with dozens of cores easier to program.
A handful of startups have pursued massively parallel architectures of various sorts, attacking high-end markets traditionally served by FPGAs and DSPs. However, few to date have gained much noticeable market traction. For its part, Tilera (Westborough, Mass.) claims it already has design wins with more than 10 primarily small or midsize networking and video OEMs, including 3Com Corp.
Tilera's chief technologist, Anant Agarwal, a longtime multicore researcher at MIT, admits his company's tools are no panacea for the formidable computer science problems that underlie programming massively parallel architectures. "There is no silver bullet in multicore programming," he said.
Nevertheless, the company appears to be striking the target with a well-aimed arrow.
"A lot of customers have taken off-the-shelf code, compiled it and run it in minutes," said Agarwal. "Our mesh interconnect and software tools are quite ground-breaking and applicable to all embedded applications."
Tilera's approach is straightforward. Its individual cores are full-fledged general-purpose processors, each capable of running a symmetric multiprocessing version of Linux. Each core also has an embedded switch for linking to any of the other cores on the die connected on a mesh network.
Thus, OEMs can port their apps readily to one or several of the cores. They can then use the startup's optimization tools to identify where bottlenecks exist in the programs and a set of streaming communications libraries to help add more cores to the mix to open up memory or processing bandwidth as needed. In a handful of applications for such jobs as packet sniffing and digital video encoding, customers have been able to use all 64 cores on the die, said Agarwal.
"Every one of these startups I see requires a two-step software development process, but this one sounds like it could be simpler," said Will Strauss, principal of market watcher Forward Concepts (Tempe, Ariz.), who was briefed on the chip.
Tilera's approach is unique in part because each of its cores has the interrupt and cache structures needed to support a full operating system, Strauss said. Others tend to use simplified cores and novel programming approaches.
"They have a value proposition because it takes five of TI's best DSPs at $200 a crack to handle real-time H.264 encoding," he added.
Tilera's Eclipse-based development environment currently supports Linux and a standard C compiler. Future software releases will support C++, other languages and operating systems.
Success for these massively parallel processors "comes down to how effective the software tools are," said Linley Gwennap, principal of consulting firm The Linley Group (Mountain View, Calif.).
"You can slap dozens or even hundreds of cores on a die. Interconnecting them is a bit difficult, but the real problem is developing a way software can use all these processors," said Gwennap. "It's hard to find any automated software that uses more than a handful of processors."
Indeed, even one of the organizers of Hot Chips confided that this year's event will feature papers on many multicore chips, but far too little novel work on multicore programming models.
Only one of Tilera's customers was willing to talk about its experience with the chip so far. Top Layer (Westboro, Mass.) plans to use the Tile64 in its next-generation network security appliance, said Michael Paquette, the company's chief strategy officer.
"Our current architecture is well-suited to the Tilera approach because it is made up of ASICs and FPGAs that make it essentially a multiprocessor system," Paquette said. "We are planning to port the apps from some of those processors to multiple Tilera cores in our next-generation platform."
Top Layer's developers are just now starting to work with the Tilera tools to expand their applications across all 64 cores in the processor. The company chose the Tile64 in part because Tilera plans to deliver a 120-core device in 2009, assuring the OEM that ships less than 10,000 of its network appliances a year a long road map for its next-generation design.