LONDON Two EDA companies, Cadence Design Systems Inc. and Mentor Graphics Corp., have joined forces to promote a common approach to the verification of design files based on the SystemVerilog language.
The two companies have called it the "Open Verification Methodology" or OVM, to emphasize that it is an open-source and freely available approach. Available under an Apache License, Version 2.0 open-source license, OVM is a superset of the previous Cadence approach to SystemVerilog verification, called URM, and Mentor's previous approach, called AVM, with some additional features, executives from Cadence and Mentor said.
While the extra system-level features are important, the most important aspect of OVM is standardization on a common approach by two of the big three EDA companies, according to Dennis Brophy, director of business development at Mentor, and Steve Glaser, corporate vice president of verification marketing at Cadence.
It will deliver portability of files and interoperability with any simulator supporting the IEEE 1800 SystemVerilog standard, the executives said.
In addition it extends verification IP by allowing for containment of code blocks and clustering to provide support of block-to-chip-to-system hierarchy and reuse while supporting description at transaction-and register-transfer levels of abstraction (TLM and RTL).
"People use other languages for design - SystemC is a good example - and we need to support SystemC and SystemVerilog working together at the TLM as well as the RTL," said Glaser.