Startup Align Engineering has come out of its stealth period with what it claims is a circuit technology breakthrough for simple chip-to-chip communication using a single-clock domain. Align Lock Loop (ALL) is said to provide a cost-effective alternative to today's serializer/deserializer (serdes) I/O designs.
"In the evolution of I/O, the goal has always been higher speed with fewer pins," said Align Engineering founder and CEO Bryan Hoyer (Friday Harbor, Wash.). "Align offers a viable alternative to complex serdes I/O."
A serializer/deserializer is a transceiver that converts parallel data to serial data and vice versa. Align's technology turns every low-voltage differential signaling (LVDS) pair into a complete serdes solution in a single clock domain, eliminating multiple expensive clock data recovery (CDR) devices and associated phase-locked loops (PLLs), Hoyer said. LVDS can run at very high speeds over inexpensive, twisted-pair copper cables.
"Creating a single-clock environment has a positive impact on initial design simulation, cost and simplicity. It is also offers a substantial improvement in interoperability and time-to-market," said Hoyer.
In operation, the Align Lock Loops' master circuit transmits encoded data, and the slave circuit aligns the data and transmits it back to the master using the recovered clock. "The advantage of such a scheme is that a master CDR and PLL are eliminated, and the design and verification takes place in a single clock domain," said Hoyer.
ALLs are protocol-agnostic and complement Ethernet PCI Express (PCIe) and other backplane specs, he said, describing the loops as "ideal for chip-to-chip, board-to-board and chips-off-board applications."
Hoyer cited a typical two-chip example to illustrate ALLs' claimed benefits. The true-and-true methods for connecting an FPGA with an A/D converter, he said, are either too I/O-intensive (the source-synchronous method) or too expensive (the common serdes method). By contrast, ALLs use a pair of I/Os between the chips with a phase control and phase adjuster circuit in the respective transmitting and receiving circuits of the two chips. The technique is only limited by the speed of the I/O, said Hoyer; as I/O gets faster, so do the ALLs.
"We are in discussions with FPGA companies and other companies where a partnership to bring the technology forward makes sense," said Hoyer, an industry veteran who sold his startup Boulder Creek Engineering, a test and measurement company, to Altera in 1999. Recently, Hoyer helped launched Samplify Systems, a venture-backed startup selling compression IP. Today, Align Engineering has sparse visibility, but Hoyer is sure his company's efforts will win attention.
"Our business model is straightforward," he said. "We want to prove our technology in silicon with a technology demonstration in the fourth quarter. We are going to provide turnkey solutions, work with IP partners and FPGA vendors and at the same time increase performance of our technology. "
Hoyer also said he is eager to gauge interest among the end-user community to provide the needed inputs for chip vendors to incorporate the single-clock methodology in future ICs.